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Searched refs:INTC (Results 1 – 11 of 11) sorted by relevance

/arch/mips/pci/
Dfixup-sni.c26 #define INTC PCIMT_IRQ_INTC macro
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
76 { 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */
77 { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
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Dfixup-ip32.c23 #define INTC MACEPCI_SHARED1_IRQ macro
30 {0, INTA0, INTB, INTC, INTD},
31 {0, INTA1, INTC, INTD, INTB},
32 {0, INTA2, INTD, INTB, INTC},
Dfixup-capcella.c19 #define INTC PC104PLUS_INTC_IRQ macro
25 [14] = { -1, INTA, INTB, INTC, INTD }
/arch/arm/mach-iop32x/
Dem7210.c76 #define INTC IRQ_IOP32X_XINT2 macro
90 {INTC, INTC, INTC, INTC}, /* GD31244 */ in em7210_pci_map_irq()
92 {INTD, INTC, INTA, INTA}, /* NEC USB */ in em7210_pci_map_irq()
Dglantank.c71 #define INTC IRQ_IOP32X_XINT2 macro
85 {INTC, INTC, INTC, INTC}, /* USB (NEC) */ in glantank_pci_map_irq()
/arch/arc/boot/dts/
Daxc001.dtsi83 * This INTC is actually connected to DW APB GPIO
84 * which acts as a wire between MB INTC and CPU INTC.
85 * GPIO INTC is configured in platform init code
86 * and here we mimic direct connection from MB INTC to
87 * CPU INTC, thus we set "interrupts = <7>" instead of
Daxc003_idu.dtsi127 * This INTC is actually connected to DW APB GPIO
128 * which acts as a wire between MB INTC and CPU INTC.
129 * GPIO INTC is configured in platform init code
130 * and here we mimic direct connection from MB INTC to
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
/arch/powerpc/boot/dts/
Dholly.dts157 | The INTA, INTB, INTC, INTD are shared.
Dkatmai.dts309 * INTC: J2: 1-2
/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi819 <0 0 0 3 &pcie_intc 2>, /* INTC */
Duniphier-ld20.dtsi922 <0 0 0 3 &pcie_intc 2>, /* INTC */