Searched refs:ISR (Results 1 – 8 of 8) sorted by relevance
| /arch/arc/kernel/ |
| D | entry-compact.S | 145 ; Level 2 ISR: Can interrupt a Level 1 ISR
152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
156 ; -L2 interrupts L1 (before L1 ISR could run)
180 ; setup params for Linux common ISR and invoke it
223 ; Level 1 ISR
358 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
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| /arch/m68k/68000/ |
| D | ints.c | 82 unsigned long pend = ISR; in process_int()
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| /arch/m68k/include/asm/ |
| D | MC68EZ328.h | 283 #define ISR LONG_REF(ISR_ADDR) macro
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| D | MC68328.h | 360 #define ISR LONG_REF(ISR_ADDR) macro
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| D | MC68VZ328.h | 292 #define ISR LONG_REF(ISR_ADDR) macro
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| /arch/arm/crypto/ |
| D | aes-neonbs-core.S | 580 ISR: .quad 0x0504070602010003, 0x0f0e0d0c080b0a09 label
597 __ldr q12, ISR
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| /arch/arm64/crypto/ |
| D | aes-neonbs-core.S | 377 ISR: .octa 0x0f0e0d0c080b0a090504070602010003 label
500 ldr q24, ISR
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| /arch/x86/kvm/ |
| D | trace.h | 245 AREG(EOI), AREG(RRR), AREG(LDR), AREG(DFR), AREG(SPIV), AREG(ISR), \
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