Searched refs:L1D (Results 1 – 25 of 32) sorted by relevance
12
| /arch/arm/kernel/ |
| D | perf_event_v7.c | 179 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
182 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
229 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
230 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
231 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
232 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
266 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
267 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
[all …]
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| D | perf_event_v6.c | 96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
160 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
161 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
162 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
|
| D | perf_event_xscale.c | 73 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
74 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
75 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
76 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
|
| /arch/arm64/kernel/ |
| D | perf_event.c | 60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
84 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
112 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
113 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
121 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
[all …]
|
| /arch/alpha/kernel/ |
| D | setup.c | 1279 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1289 L1D = L1I; in determine_cpu_caches()
1310 L1I = L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1325 L1I = L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1351 L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1354 L1D = CSHAPE(16*1024, 5, 1); in determine_cpu_caches()
1377 L1I = L1D = CSHAPE(64*1024, 6, 2); in determine_cpu_caches()
1384 L1I = L1D = CSHAPE(64*1024, 6, 2); in determine_cpu_caches()
1391 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1396 alpha_l1d_cacheshape = L1D; in determine_cpu_caches()
|
| /arch/powerpc/perf/ |
| D | e6500-pmu.c | 36 [C(L1D)] = {
|
| D | e500-pmu.c | 39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power10-pmu.c | 348 [C(L1D)] = {
449 [C(L1D)] = {
|
| D | generic-compat-pmu.c | 176 [ C(L1D) ] = {
|
| D | mpc7450-pmu.c | 366 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power8-pmu.c | 257 [ C(L1D) ] = {
|
| D | ppc970-pmu.c | 439 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power7-pmu.c | 340 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power9-pmu.c | 328 [ C(L1D) ] = {
|
| /arch/mips/kernel/ |
| D | perf_event_mipsxx.c | 1019 [C(L1D)] = {
1100 [C(L1D)] = {
1175 [C(L1D)] = {
1215 [C(L1D)] = {
1270 [C(L1D)] = {
1333 [C(L1D)] = {
1386 [C(L1D)] = {
1444 [C(L1D)] = {
1484 [C(L1D)] = {
|
| /arch/arc/include/asm/ |
| D | perf_event.h | 127 [C(L1D)] = {
|
| /arch/sh/kernel/cpu/sh4/ |
| D | perf_event.c | 91 [ C(L1D) ] = {
|
| /arch/x86/events/intel/ |
| D | p6.c | 28 [ C(L1D) ] = {
|
| D | knc.c | 26 [ C(L1D) ] = {
|
| /arch/sh/kernel/cpu/sh4a/ |
| D | perf_event.c | 116 [ C(L1D) ] = {
|
| /arch/x86/events/zhaoxin/ |
| D | core.c | 51 [C(L1D)] = {
155 [C(L1D)] = {
|
| /arch/x86/events/amd/ |
| D | core.c | 26 [ C(L1D) ] = {
130 [C(L1D)] = {
|
| /arch/riscv/kernel/ |
| D | perf_event.c | 56 [C(L1D)] = {
|
| /arch/nds32/include/asm/ |
| D | pmu.h | 244 [C(L1D)] = {
|
| /arch/sparc/kernel/ |
| D | perf_event.c | 221 [C(L1D)] = {
359 [C(L1D)] = {
494 [C(L1D)] = {
631 [C(L1D)] = {
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