Searched refs:MSTP (Results 1 – 3 of 3) sorted by relevance
/arch/sh/kernel/cpu/sh4a/ |
D | clock-sh7343.c | 125 #define MSTP(_parent, _reg, _bit, _flags) \ macro 139 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 140 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 141 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 142 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 143 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 144 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 145 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 146 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 147 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), [all …]
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D | clock-sh7366.c | 128 #define MSTP(_parent, _reg, _bit, _flags) \ macro 142 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 143 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 144 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 145 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 146 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 147 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 148 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 149 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 150 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), [all …]
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/arch/arm/boot/dts/ |
D | r7s72100.dtsi | 407 /* MSTP clocks */
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