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Searched refs:Op1 (Results 1 – 5 of 5) sorted by relevance

/arch/arm64/kvm/
Dsys_regs.h17 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
22 u8 Op1; member
32 .Op1 = ((esr) >> 14) & 0x7, \
50 u8 Op1; member
93 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
160 if (i1->Op1 != i2->Op1) in cmp_sys_reg()
161 return i1->Op1 - i2->Op1; in cmp_sys_reg()
212 #define Op1(_x) .Op1 = _x macro
219 Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
Dsys_regs.c197 switch (p->Op1) { in access_gic_sgi()
1362 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1829 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1831 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1833 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1835 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1838 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1847 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1849 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1853 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
[all …]
Dtrace_handle_exit.h169 __field(u8, Op1)
181 __entry->Op1 = reg->Op1;
189 __entry->Op0, __entry->Op1, __entry->CRn,
/arch/arm/include/asm/vdso/
Dcp15.h14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
16 #define __ACCESS_CP15_64(Op1, CRm) \ argument
17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c324 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \