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Searched refs:Op2 (Results 1 – 6 of 6) sorted by relevance

/arch/arm64/kvm/
Dsys_regs.c208 switch (p->Op2) { in access_gic_sgi()
711 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); in access_pmceid()
741 if (r->Op2 == 2) { in access_pmu_evcntr()
748 } else if (r->Op2 == 0) { in access_pmu_evcntr()
766 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); in access_pmu_evcntr()
795 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { in access_pmu_evtyper()
800 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); in access_pmu_evtyper()
835 if (r->Op2 & 0x1) { in access_pmcnten()
863 if (r->Op2 & 0x1) in access_pminten()
1362 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
[all …]
Dsys_regs.h18 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
25 u8 Op2; member
35 .Op2 = ((esr) >> 17) & 0x7, \
53 u8 Op2; member
93 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
166 return i1->Op2 - i2->Op2; in cmp_sys_reg()
215 #define Op2(_x) .Op2 = _x macro
221 Op2(sys_reg_Op2(reg))
Dtrace_handle_exit.h172 __field(u8, Op2)
184 __entry->Op2 = reg->Op2;
190 __entry->CRm, __entry->Op2,
Dvgic-sys-reg-v3.c203 u8 idx = r->Op2 & 3; in access_gic_aprn()
/arch/arm/include/asm/vdso/
Dcp15.h14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c324 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \