/arch/x86/events/intel/ |
D | ds.c | 63 #define P(a, b) PERF_MEM_S(a, b) macro 64 #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) 65 #define LEVEL(x) P(LVLNUM, x) 66 #define REM P(REMOTE, REMOTE) 67 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) 71 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 72 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 73 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ 74 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ 75 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ [all …]
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/arch/alpha/include/asm/ |
D | switch_to.h | 9 #define switch_to(P,N,L) \ argument 11 (L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
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/arch/powerpc/perf/ |
D | isa207-common.h | 273 #define P(a, b) PERF_MEM_S(a, b) macro 274 #define PH(a, b) (P(LVL, HIT) | P(a, b)) 275 #define PM(a, b) (P(LVL, MISS) | P(a, b))
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D | isa207-common.c | 238 ret |= P(SNOOP, HIT); in isa207_find_source() 243 ret |= P(SNOOP, HIT); in isa207_find_source() 245 ret |= P(SNOOP, HITM); in isa207_find_source() 250 ret |= P(SNOOP, HIT); in isa207_find_source() 252 ret |= P(SNOOP, HITM); in isa207_find_source() 301 dsrc->val |= P(OP, LOAD); in isa207_get_mem_data_src() 304 dsrc->val |= P(OP, STORE); in isa207_get_mem_data_src() 307 dsrc->val |= P(OP, NA); in isa207_get_mem_data_src() 311 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); in isa207_get_mem_data_src()
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/arch/arm/boot/dts/ |
D | am437x-l4.dtsi | 156 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 189 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 218 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 244 /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ 356 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 394 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 433 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 469 /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ 707 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 735 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ [all …]
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D | omap4-l4.dtsi | 56 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ 156 /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ 194 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 256 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 285 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 332 /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ 403 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 437 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ 474 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ 495 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ [all …]
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D | omap5-l4.dtsi | 185 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 233 /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ 286 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 314 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 362 /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ 447 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 504 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ 605 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ 644 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ 1074 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ [all …]
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D | omap4-l4-abe.dtsi | 99 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 132 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 165 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 197 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 235 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 268 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 294 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 328 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 359 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 390 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ [all …]
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D | dra7-l4.dtsi | 209 /* Domains (P, C): core_pwrdm, dma_clkdm */ 249 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 316 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 404 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 423 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 450 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 483 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 1154 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1183 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1210 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ [all …]
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D | imx6qdl-dhcom-drc02.dtsi | 86 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property 87 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via 95 rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ 118 * P: uart5 rs485-tx-en
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D | omap5-l4-abe.dtsi | 99 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 132 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 165 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 217 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 257 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 291 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 323 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 355 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 386 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 446 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
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D | pxa2xx.dtsi | 13 groups = PMGROUP(P ## pin); \ 18 groups = PMGROUP(P ## pin); \ 24 groups = PMGROUP(P ## pin); \
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D | am33xx-l4.dtsi | 151 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 195 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 228 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 254 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 368 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 406 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 445 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 1101 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1132 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1165 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ [all …]
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D | imx6q-kp-tpc.dts | 12 model = "Freescale i.MX6 Qwuad K+P TPC Board";
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D | imx53-kp-hsc.dts | 11 model = "K+P imx53 HSC";
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D | tegra30-asus-nexus7-tilapia.dtsi | 31 <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>, 231 enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; 232 firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
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D | aspeed-bmc-opp-zaius.dts | 108 mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>; 522 gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; 528 gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; 534 gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
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D | aspeed-bmc-opp-swift.dts | 208 clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; 209 data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 210 mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; 211 enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; 212 trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
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D | am57-pruss.dtsi | 22 /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ 131 /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
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/arch/mips/kernel/ |
D | perf_event_mipsxx.c | 67 P = 2, enumerator 939 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 948 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 1054 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 1055 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 1058 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 1059 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 1135 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 1136 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, 1139 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, [all …]
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/arch/m68k/fpsp040/ |
D | stwotox.S | 61 | 3. Calculate P where 1 + P approximates exp(r): 62 | P = r + r*r*(A1+r*(A2+...+r*A5)).
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D | ssin.S | 488 |--we want P+p = W+w but |p| <= half ulp of P 489 |--Then, we need to compute A := R-P and a := r-p 490 faddx %fp5,%fp3 | ...FP3 is P 491 fsubx %fp3,%fp4 | ...W-P 493 fsubx %fp3,%fp0 | ...FP0 is A := R - P 494 faddx %fp5,%fp4 | ...FP4 is p = (W-P)+w
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/arch/arm64/boot/dts/qcom/ |
D | msm8994-angler-rev-101.dts | 15 model = "Huawei Nexus 6P";
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D | apq8096-db820c.dts | 23 * P HSEC = Primary High Speed External Connector 278 "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ 280 "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ 282 "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ 283 "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ 350 "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ 351 "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ 352 "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ 353 "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
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/arch/s390/crypto/ |
D | crc32be-vx.S | 67 .quad 0x104C11DB7, 0 # P(x)
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