Searched refs:PSR_I_BIT (Results 1 – 25 of 30) sorted by relevance
12
| /arch/arm64/include/asm/ |
| D | daifflags.h | 16 #define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT)
17 #define DAIF_ERRCTX (PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
18 #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
50 flags |= PSR_I_BIT | PSR_F_BIT; in local_daif_save_flags()
69 bool irq_disabled = flags & PSR_I_BIT; in local_daif_restore()
72 (read_sysreg(daif) & (PSR_I_BIT | PSR_F_BIT)) != (PSR_I_BIT | PSR_F_BIT)); in local_daif_restore()
89 flags &= ~(PSR_I_BIT | PSR_F_BIT); in local_daif_restore()
|
| D | ptrace.h | 20 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
22 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
243 (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
|
| D | cpuidle.h | 35 write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
|
| D | irqflags.h | 86 "and %w0, %w1, #" __stringify(PSR_I_BIT), in arch_irqs_disabled_flags()
|
| D | efi.h | 48 #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
|
| D | kvm_arm.h | 367 #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
|
| /arch/arm/kernel/ |
| D | fiqasm.S | 26 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
39 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
|
| D | entry-armv.S | 310 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
311 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
315 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
316 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
324 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
325 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
329 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
330 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
|
| D | iwmmxt.S | 198 orr r2, ip, #PSR_I_BIT @ disable interrupts
250 orr r2, ip, #PSR_I_BIT @ disable interrupts
288 orr r2, ip, #PSR_I_BIT @ disable interrupts
355 orr ip, r2, #PSR_I_BIT @ disable interrupts
|
| D | setup.c | 574 PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), in cpu_init()
576 PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE), in cpu_init()
578 PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE), in cpu_init()
580 PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), in cpu_init()
582 PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE) in cpu_init()
|
| /arch/arm/include/asm/ |
| D | ptrace.h | 48 (!((regs)->ARM_cpsr & PSR_I_BIT))
66 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { in valid_user_regs()
|
| D | efi.h | 35 (PSR_J_BIT | PSR_E_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | \
|
| D | irqflags.h | 19 #define IRQMASK_I_BIT PSR_I_BIT
|
| D | assembler.h | 102 msr cpsr_c, #PSR_I_BIT | SVC_MODE
192 tst \oldcpsr, #PSR_I_BIT
377 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
392 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
|
| /arch/arm/mach-s3c/ |
| D | sleep-s3c24xx.S | 42 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
|
| D | sleep-s3c64xx.S | 40 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
|
| /arch/arm/mach-rockchip/ |
| D | sleep.S | 20 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
|
| /arch/arm/include/uapi/asm/ |
| D | ptrace.h | 79 #define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */ macro
|
| /arch/arm64/include/uapi/asm/ |
| D | ptrace.h | 46 #define PSR_I_BIT 0x00000080 macro
|
| /arch/arm/mm/ |
| D | proc-feroceon.S | 250 orr r3, r2, #PSR_I_BIT
296 orr r3, r2, #PSR_I_BIT
328 orr r3, r2, #PSR_I_BIT
359 orr r3, r2, #PSR_I_BIT
|
| D | proc-xsc3.S | 107 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
448 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
|
| /arch/arm64/kvm/hyp/nvhe/ |
| D | hyp-init.S | 203 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
|
| D | host.S | 80 mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
|
| /arch/arm64/kvm/hyp/ |
| D | exception.c | 135 new |= PSR_I_BIT; in get_except64_cpsr()
|
| /arch/arm64/kernel/ |
| D | process.c | 191 pstate & PSR_I_BIT ? 'I' : 'i', in print_pstate()
|
12