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Searched refs:RD (Results 1 – 25 of 26) sorted by relevance

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/arch/x86/crypto/
Dserpent-sse2-i586-asm_32.S30 #define RD %xmm3 macro
513 read_blocks(%eax, RA, RB, RC, RD, RT0, RT1, RE);
515 K(RA, RB, RC, RD, RE, 0);
516 S0(RA, RB, RC, RD, RE); LK(RC, RB, RD, RA, RE, 1);
517 S1(RC, RB, RD, RA, RE); LK(RE, RD, RA, RC, RB, 2);
518 S2(RE, RD, RA, RC, RB); LK(RB, RD, RE, RC, RA, 3);
519 S3(RB, RD, RE, RC, RA); LK(RC, RA, RD, RB, RE, 4);
520 S4(RC, RA, RD, RB, RE); LK(RA, RD, RB, RE, RC, 5);
521 S5(RA, RD, RB, RE, RC); LK(RC, RA, RD, RE, RB, 6);
522 S6(RC, RA, RD, RE, RB); LK(RD, RB, RA, RE, RC, 7);
[all …]
Dserpent-sse2-x86_64-asm_64.S636 K2(RA, RB, RC, RD, RE, 0);
637 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
638 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
639 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
640 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
641 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
642 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
643 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
644 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
645 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
[all …]
Dserpent-avx2-asm_64.S567 K2(RA, RB, RC, RD, RE, 0);
568 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
569 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
570 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
571 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
572 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
573 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
574 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
575 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
576 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
[all …]
Dserpent-avx-x86_64-asm_64.S567 K2(RA, RB, RC, RD, RE, 0);
568 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
569 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
570 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
571 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
572 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
573 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
574 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
575 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
576 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
[all …]
Dtwofish-avx-x86_64-asm_64.S189 encrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l); \
190 encrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l);
193 encrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l); \
194 encrypt_round(((2*n) + 1), RC, RD, RA, RB, dummy, dummy);
197 decrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l); \
198 decrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l);
201 decrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l); \
202 decrypt_round((2*n), RA, RB, RC, RD, dummy, dummy);
Dcast6-avx-x86_64-asm_64.S153 qop(RD, RC, 1); \
162 qop(RA, RD, 1);
166 qop(RA, RD, 1); \
175 qop(RD, RC, 1);
Dsha1_avx2_x86_64_asm.S111 .set RD, REG_RD define
332 .set RE, RD
333 .set RD, RC define
/arch/mips/mm/
Duasm-mips.c52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
72 [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
73 [insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
74 [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
75 [insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
77 [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
80 RS | RT | RD},
82 [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
83 [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
[all …]
Duasm-micromips.c43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
56 [insn_cfcmsa] = {M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE},
58 [insn_ctcmsa] = {M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE},
74 [insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
75 [insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
87 [insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
90 [insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
93 [insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
94 [insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
[all …]
Duasm.c19 RD = 0x004, enumerator
/arch/sparc/crypto/
Dopcodes.h14 #define RD(x) (FPD_ENCODE(x) << 25) macro
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
35 .word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));
37 .word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));
39 .word (F3F(2, 0x19, 4)|RS1(a)|RS2(b)|RS3(c)|RD(d));
41 .word (F3F(2, 0x19, 5)|RS1(a)|RS2(b)|RS3(c)|RD(d));
43 .word (F3F(2, 0x19, 6)|RS1(a)|RS2(b)|RS3(c)|RD(d));
45 .word (F3F(2, 0x19, 7)|RS1(a)|RS2(b)|RS3(c)|RD(d));
[all …]
/arch/sparc/net/
Dbpf_jit_comp_32.c25 #define RD(X) ((X) << 25) macro
69 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
113 *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \
118 *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \
123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
140 *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \
161 _insn |= RS1(r_A) | RD(r_A); \
175 *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \
184 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
[all …]
Dbpf_jit_comp_64.c54 #define RD(X) ((X) << 25) macro
137 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
263 emit(OR | RS1(G0) | RS2(from) | RD(to), ctx); in emit_reg_move()
284 emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); in emit_set_const_sext()
290 emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx); in emit_alu()
295 emit(opcode | RS1(a) | RS2(b) | RD(c), ctx); in emit_alu3()
304 insn |= RS1(dst) | RD(dst); in emit_alu_K()
323 insn |= RS1(src) | RD(dst); in emit_alu3_K()
340 emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx); in emit_loadimm32()
[all …]
/arch/powerpc/crypto/
Dsha1-powerpc-asm.S30 #define RD(t) ((((t)+1)%6)+7) macro
40 andc r0,RD(t),RB(t); \
53 andc r0,RD(t),RB(t); \
70 xor r6,r6,RD(t); \
80 xor r6,r6,RD(t); \
92 and r0,RB(t),RD(t); \
96 and r0,RC(t),RD(t); \
134 lwz RD(0),12(r3) /* D */
175 add RD(0),RD(80),r19
183 stw RD(0),12(r3)
/arch/sparc/kernel/
Dvisemul.c138 #define RD(INSN) (((INSN) >> 25) & 0x1f) macro
299 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in edge()
350 store_reg(regs, rd_val, RD(insn)); in edge()
377 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in array()
403 store_reg(regs, rd_val, RD(insn)); in array()
410 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in bmask()
415 store_reg(regs, rd_val, RD(insn)); in bmask()
445 *fpd_regaddr(f, RD(insn)) = rd_val; in bshuffle()
456 rd = fpd_regaddr(f, RD(insn)); in pdist()
503 *fps_regaddr(f, RD(insn)) = rd_val; in pformat()
[all …]
/arch/arm/mach-mv78xx0/
DKconfig23 bool "Marvell RD-78x00-mASA Reference Design"
26 Marvell RD-78x00-mASA Reference Design.
/arch/arm/boot/dts/
Darmada-382-rd-ac3x-48g4x2xl.dts4 * (RD-AC3X-48G4X2XL)
15 model = "Marvell Armada 382 RD-AC3X";
Darmada-xp-axpwifiap.dts3 * Device Tree file for Marvell RD-AXPWiFiAP.
21 model = "Marvell RD-AXPWiFiAP";
Darmada-388-rd.dts4 * (RD-88F6820-AP)
Darmada-370-rd.dts4 * (RD-88F6710-A1)
Darmada-388-gp.dts4 * (RD-88F6820-GP)
/arch/sh/include/mach-ecovec24/mach/
Dpartner-jet-setup.txt9 LIST "> RD zImage, 0xa8800000"
14 LIST "> RD romImage, 0"
/arch/arm/mach-orion5x/
DKconfig154 Marvell Orion-VoIP GE (88F5181L) RD.
160 Marvell Orion-VoIP FXO (88F5181L) RD.
166 Marvell Orion-1-90 (88F6183) AP GE RD.
/arch/sh/include/mach-kfr2r09/mach/
Dpartner-jet-setup.txt8 LIST "> RD zImage, 0xa8800000"
13 LIST "> RD romImage, 0"
/arch/mips/kernel/
Dtraps.c504 #define RD 0x0000f800 macro
667 int rd = (opcode & RD) >> 11; in simulate_rdhwr_normal()
723 int rd = (opcode & RD) >> 11; in simulate_loongson3_cpucfg()

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