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Searched refs:S3C2410_SRCPND (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-s3c/
Dpm-core-s3c24xx.h41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
71 __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
74 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
Dirq-s3c24xx-fiq.S27 @ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
42 str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
71 str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
95 str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
Dsleep-s3c2412.S22 ldr r2, =S3C2410_SRCPND
Dregs-irq-s3c24xx.h19 #define S3C2410_SRCPND S3C2410_IRQREG(0x000) macro