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Searched refs:SC (Results 1 – 9 of 9) sorted by relevance

/arch/m68k/fpsp040/
Dsetox.S696 movew %d0,SC(%a6) | ...SC is 2^(M) in extended
697 clrw SC+2(%a6)
698 movel #0x80000000,SC+4(%a6)
699 clrl SC+8(%a6)
762 fmulx SC(%a6),%fp0
776 movel #0x80010000,SC(%a6) | ...SC is -2^(-16382)
777 movel #0x80000000,SC+4(%a6)
778 clrl SC+8(%a6)
781 faddx SC(%a6),%fp0
789 movel #0x80010000,SC(%a6)
[all …]
/arch/arm/boot/dts/
Dimx28-sps1.dts10 model = "SchulerControl GmbH, SC SPS 1";
/arch/mips/
DKconfig2080 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
2086 # CPU may reorder reads and writes beyond LL/SC
2087 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2721 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
/arch/mips/kernel/
Dtraps.c501 #define SC 0xe0000000 macro
616 if ((opcode & OPCODE) == SC) { in simulate_llsc()
Dmips-r2-to-r6-emul.c47 #define SC "sc " macro
/arch/m68k/ifpsp060/src/
Dfplsp.S7330 mov.w %d1,SC(%a6) # SC is 2^(M) in extended
7331 mov.l &0x80000000,SC+4(%a6)
7332 clr.l SC+8(%a6)
7392 fmul.x SC(%a6),%fp0
7405 mov.l &0x80010000,SC(%a6) # SC is -2^(-16382)
7406 mov.l &0x80000000,SC+4(%a6)
7407 clr.l SC+8(%a6)
7411 fadd.x SC(%a6),%fp0
7418 mov.l &0x80010000,SC(%a6)
7419 mov.l &0x80000000,SC+4(%a6)
[all …]
Dfpsp.S7203 set SC,FP_SCR0
/arch/powerpc/xmon/
Dppc-opc.c2494 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) macro
4136 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4137 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4138 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4139 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4140 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
/arch/x86/
DKconfig2781 NSC Geode SC-1100's buggy TSC, which loses time when the