Home
last modified time | relevance | path

Searched refs:XCHAL_ICACHE_LINEWIDTH (Results 1 – 10 of 10) sorted by relevance

/arch/xtensa/include/asm/
Dcacheasm.h97 XCHAL_ICACHE_LINEWIDTH 240
137 XCHAL_ICACHE_LINEWIDTH 1020
174 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
211 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
Dcache.h23 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
/arch/xtensa/variants/fsf/include/variant/
Dcore.h116 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h131 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h123 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h162 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dcore.h182 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/csp/include/variant/
Dcore.h210 #define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/de212/include/variant/
Dcore.h210 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/arch/xtensa/variants/test_kc705_be/include/variant/
Dcore.h211 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro