Home
last modified time | relevance | path

Searched refs:XCHAL_NUM_DBREAK (Results 1 – 15 of 15) sorted by relevance

/arch/xtensa/kernel/
Dhw_breakpoint.c21 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
29 return XCHAL_NUM_DBREAK; in hw_breakpoint_slots()
99 BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2); in xtensa_wsr()
113 #if XCHAL_NUM_DBREAK > 0 in xtensa_wsr()
121 #if XCHAL_NUM_DBREAK > 1 in xtensa_wsr()
184 i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp); in arch_install_hw_breakpoint()
223 i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp); in arch_uninstall_hw_breakpoint()
244 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) { in flush_ptrace_hw_breakpoint()
267 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) { in restore_dbreak()
293 if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) { in check_hw_breakpoint()
Dptrace.c379 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) in ptrace_hbptriggered()
425 (dbreak && idx >= XCHAL_NUM_DBREAK)) in ptrace_gethbpregs()
461 (dbreak && idx >= XCHAL_NUM_DBREAK)) in ptrace_sethbpregs()
Dhead.S130 .rept XCHAL_NUM_DBREAK
Dsetup.c670 XCHAL_NUM_DBREAK); in c_show()
Dentry.S851 .rept XCHAL_NUM_DBREAK
869 .rept XCHAL_NUM_DBREAK
/arch/xtensa/include/asm/
Dtraps.h108 unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
Dprocessor.h154 struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK];
/arch/xtensa/variants/fsf/include/variant/
Dcore.h328 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
Dcore.h353 #define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h393 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h443 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dcore.h489 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/csp/include/variant/
Dcore.h532 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/de212/include/variant/
Dcore.h553 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/arch/xtensa/variants/test_kc705_be/include/variant/
Dcore.h532 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro