Searched refs:__IA64_UL (Results 1 – 5 of 5) sorted by relevance
81 #define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)82 #define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)83 #define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)84 #define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)85 #define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)86 #define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)87 #define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)88 #define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)89 #define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)90 #define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)[all …]
43 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */44 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */45 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */46 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */47 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */48 #define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration50 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */51 #define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
57 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)58 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */59 #define _PAGE_PROTNONE (__IA64_UL(1) << 63)90 #define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))126 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)465 #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
23 # define __IA64_UL(x) (x)27 # define __IA64_UL(x) ((unsigned long)(x)) macro
21 #define FPSR_S2(x) (__IA64_UL(x) << 32)22 #define FPSR_S3(x) (__IA64_UL(x) << 45)