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1  /*
2   * include/asm-xtensa/coprocessor.h
3   *
4   * This file is subject to the terms and conditions of the GNU General Public
5   * License.  See the file "COPYING" in the main directory of this archive
6   * for more details.
7   *
8   * Copyright (C) 2003 - 2007 Tensilica Inc.
9   */
10  
11  
12  #ifndef _XTENSA_COPROCESSOR_H
13  #define _XTENSA_COPROCESSOR_H
14  
15  #include <variant/tie.h>
16  #include <asm/core.h>
17  #include <asm/types.h>
18  
19  #ifdef __ASSEMBLY__
20  # include <variant/tie-asm.h>
21  
22  .macro	xchal_sa_start  a b
23  	.set .Lxchal_pofs_, 0
24  	.set .Lxchal_ofs_, 0
25  .endm
26  
27  .macro	xchal_sa_align  ptr minofs maxofs ofsalign totalign
28  	.set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
29  	.set	.Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
30  .endm
31  
32  #define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
33  		 | XTHAL_SAS_CC \
34  		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE )
35  
36  .macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
37  	.if XTREGS_OPT_SIZE > 0
38  		addi	\clb, \ptr, \offset
39  		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
40  	.endif
41  .endm
42  
43  .macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
44  	.if XTREGS_OPT_SIZE > 0
45  		addi	\clb, \ptr, \offset
46  		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
47  	.endif
48  .endm
49  #undef _SELECT
50  
51  #define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
52  		 | XTHAL_SAS_NOCC \
53  		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
54  
55  .macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
56  	.if XTREGS_USER_SIZE > 0
57  		addi	\clb, \ptr, \offset
58  		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
59  	.endif
60  .endm
61  
62  .macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
63  	.if XTREGS_USER_SIZE > 0
64  		addi	\clb, \ptr, \offset
65  		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
66  	.endif
67  .endm
68  #undef _SELECT
69  
70  
71  
72  #endif	/* __ASSEMBLY__ */
73  
74  /*
75   * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
76   *
77   * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
78   *
79   */
80  
81  #define XTENSA_HAVE_COPROCESSOR(x)					\
82  	((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
83  #define XTENSA_HAVE_COPROCESSORS					\
84  	(XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
85  #define XTENSA_HAVE_IO_PORT(x)						\
86  	(XCHAL_CP_PORT_MASK & (1 << (x)))
87  #define XTENSA_HAVE_IO_PORTS						\
88  	XCHAL_CP_PORT_MASK
89  
90  #ifndef __ASSEMBLY__
91  
92  /*
93   * Additional registers.
94   * We define three types of additional registers:
95   *  ext: extra registers that are used by the compiler
96   *  cpn: optional registers that can be used by a user application
97   *  cpX: coprocessor registers that can only be used if the corresponding
98   *       CPENABLE bit is set.
99   */
100  
101  #define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...)	\
102  	__REG ## list (cc, abi, type, name, size, align)
103  
104  #define __REG0(cc,abi,t,name,s,a)	__REG0_ ## cc (abi,name)
105  #define __REG1(cc,abi,t,name,s,a)	__REG1_ ## cc (name)
106  #define __REG2(cc,abi,type,...)		__REG2_ ## type (__VA_ARGS__)
107  
108  #define __REG0_0(abi,name)
109  #define __REG0_1(abi,name)		__REG0_1 ## abi (name)
110  #define __REG0_10(name)	__u32 name;
111  #define __REG0_11(name)	__u32 name;
112  #define __REG0_12(name)
113  
114  #define __REG1_0(name)	__u32 name;
115  #define __REG1_1(name)
116  
117  #define __REG2_0(n,s,a)	__u32 name;
118  #define __REG2_1(n,s,a)	unsigned char n[s] __attribute__ ((aligned(a)));
119  #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
120  
121  typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
122  	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
123  typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
124  	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
125  
126  #if XTENSA_HAVE_COPROCESSORS
127  
128  typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
129  	__attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
130  typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
131  	__attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
132  typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
133  	__attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
134  typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
135  	__attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
136  typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
137  	__attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
138  typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
139  	__attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
140  typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
141  	__attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
142  typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
143  	__attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
144  
145  extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
146  extern void coprocessor_flush(struct thread_info*, int);
147  
148  extern void coprocessor_release_all(struct thread_info*);
149  extern void coprocessor_flush_all(struct thread_info*);
150  
151  #endif	/* XTENSA_HAVE_COPROCESSORS */
152  
153  #endif	/* !__ASSEMBLY__ */
154  #endif	/* _XTENSA_COPROCESSOR_H */
155