Searched refs:__cpu (Results 1 – 6 of 6) sorted by relevance
| /arch/mips/include/asm/mach-bcm63xx/ |
| D | bcm63xx_cpu.h | 552 #define __GEN_CPU_REGS_TABLE(__cpu) \ argument
553 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
554 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
555 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
556 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
557 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
558 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
559 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
560 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
561 [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
[all …]
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| /arch/mips/bcm63xx/ |
| D | reset.c | 20 #define __GEN_RESET_BITS_TABLE(__cpu) \ argument
21 [BCM63XX_RESET_SPI] = BCM## __cpu ##_RESET_SPI, \
22 [BCM63XX_RESET_ENET] = BCM## __cpu ##_RESET_ENET, \
23 [BCM63XX_RESET_USBH] = BCM## __cpu ##_RESET_USBH, \
24 [BCM63XX_RESET_USBD] = BCM## __cpu ##_RESET_USBD, \
25 [BCM63XX_RESET_DSL] = BCM## __cpu ##_RESET_DSL, \
26 [BCM63XX_RESET_SAR] = BCM## __cpu ##_RESET_SAR, \
27 [BCM63XX_RESET_EPHY] = BCM## __cpu ##_RESET_EPHY, \
28 [BCM63XX_RESET_ENETSW] = BCM## __cpu ##_RESET_ENETSW, \
29 [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
[all …]
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| /arch/sparc/include/asm/ |
| D | percpu_64.h | 15 #define __per_cpu_offset(__cpu) \ argument
16 (trap_block[(__cpu)].__per_cpu_base)
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| D | cpudata_32.h | 29 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu)) argument
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| D | cpudata_64.h | 35 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu)) argument
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| /arch/sparc/kernel/ |
| D | irq_64.c | 107 #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) argument
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