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/arch/mips/kvm/
Dmsa.S20 st_d 0, VCPU_FPR0, a0
21 st_d 1, VCPU_FPR1, a0
22 st_d 2, VCPU_FPR2, a0
23 st_d 3, VCPU_FPR3, a0
24 st_d 4, VCPU_FPR4, a0
25 st_d 5, VCPU_FPR5, a0
26 st_d 6, VCPU_FPR6, a0
27 st_d 7, VCPU_FPR7, a0
28 st_d 8, VCPU_FPR8, a0
29 st_d 9, VCPU_FPR9, a0
[all …]
Dfpu.S31 sdc1 $f1, VCPU_FPR1(a0)
32 sdc1 $f3, VCPU_FPR3(a0)
33 sdc1 $f5, VCPU_FPR5(a0)
34 sdc1 $f7, VCPU_FPR7(a0)
35 sdc1 $f9, VCPU_FPR9(a0)
36 sdc1 $f11, VCPU_FPR11(a0)
37 sdc1 $f13, VCPU_FPR13(a0)
38 sdc1 $f15, VCPU_FPR15(a0)
39 sdc1 $f17, VCPU_FPR17(a0)
40 sdc1 $f19, VCPU_FPR19(a0)
[all …]
/arch/riscv/kernel/
Dfpu.S24 add a0, a0, a2
28 fsd f0, TASK_THREAD_F0_F0(a0)
29 fsd f1, TASK_THREAD_F1_F0(a0)
30 fsd f2, TASK_THREAD_F2_F0(a0)
31 fsd f3, TASK_THREAD_F3_F0(a0)
32 fsd f4, TASK_THREAD_F4_F0(a0)
33 fsd f5, TASK_THREAD_F5_F0(a0)
34 fsd f6, TASK_THREAD_F6_F0(a0)
35 fsd f7, TASK_THREAD_F7_F0(a0)
36 fsd f8, TASK_THREAD_F8_F0(a0)
[all …]
Dcrash_save_regs.S14 REG_S ra, PT_RA(a0) /* x1 */
15 REG_S sp, PT_SP(a0) /* x2 */
16 REG_S gp, PT_GP(a0) /* x3 */
17 REG_S tp, PT_TP(a0) /* x4 */
18 REG_S t0, PT_T0(a0) /* x5 */
19 REG_S t1, PT_T1(a0) /* x6 */
20 REG_S t2, PT_T2(a0) /* x7 */
21 REG_S s0, PT_S0(a0) /* x8/fp */
22 REG_S s1, PT_S1(a0) /* x9 */
23 REG_S a0, PT_A0(a0) /* x10 */
[all …]
/arch/mips/kernel/
Dr4k_fpu.S47 fpu_save_double a0 t0 t1 # clobbers t1
59 fpu_restore_double a0 t0 t1 # clobbers t1
70 msa_save_all a0
78 msa_restore_all a0
118 EX sdc1 $f1, 8(a0)
119 EX sdc1 $f3, 24(a0)
120 EX sdc1 $f5, 40(a0)
121 EX sdc1 $f7, 56(a0)
122 EX sdc1 $f9, 72(a0)
123 EX sdc1 $f11, 88(a0)
[all …]
Docteon_switch.S28 LONG_S t1, THREAD_STATUS(a0)
29 cpu_save_nonscratch a0
30 LONG_S ra, THREAD_REG31(a0)
43 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
88 move v0, a0
106 sd t0, OCTEON_CP2_CRC_IV(a0)
107 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
110 sd t2, OCTEON_CP2_CRC_POLY(a0)
115 sd t0, OCTEON_CP2_LLM_DAT(a0)
118 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
[all …]
Dcps-vec-ns16550.S40 UART_S a0, UART_TX_OFS(t9)
53 move s6, a0
55 1: lb a0, 0(s6)
56 beqz a0, 2f
72 andi a0, a0, 0xf
74 blt a0, 10, 1f
76 addiu a0, a0, -10
77 1: addu a0, a0, t0
90 move s2, a0
91 srl a0, a0, 4
[all …]
Dr2300_fpu.S43 fpu_save_single a0, t1 # clobbers t1
51 fpu_restore_single a0, t1 # clobbers t1
70 EX2(s.d $f0, 0(a0))
71 EX2(s.d $f2, 16(a0))
72 EX2(s.d $f4, 32(a0))
73 EX2(s.d $f6, 48(a0))
74 EX2(s.d $f8, 64(a0))
75 EX2(s.d $f10, 80(a0))
76 EX2(s.d $f12, 96(a0))
77 EX2(s.d $f14, 112(a0))
[all …]
Dbmips_5xxx_init.S122 mfc0 a0, CP0_CONFIG, 1
123 move t0, a0
134 srl a0, a0, IS_SHIFT
135 and a0, a0, IS_MASK
140 sllv v0, v0, a0
150 move a0, t0
152 srl a0, a0, IL_SHIFT
153 and a0, a0, IL_MASK
155 beqz a0, no_i_cache
160 addi a0, a0, 1
[all …]
/arch/xtensa/kernel/
Dvectors.S77 s32i a0, a2, PT_AREG0 # save a0 to ESF
78 rsr a0, exccause # retrieve exception cause
79 s32i a0, a2, PT_DEPC # mark it as a regular exception
80 addx4 a0, a0, a3 # find entry in table
81 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
83 jx a0
104 s32i a0, a2, PT_AREG0 # save a0 to ESF
105 rsr a0, exccause # retrieve exception cause
106 s32i a0, a2, PT_DEPC # mark it as a regular exception
107 addx4 a0, a0, a3 # find entry in table
[all …]
Dentry.S135 rsr a0, depc
137 s32i a0, a2, PT_AREG2
208 ffs_ws a0, a3 # number of frames to the '1' from left
215 slli a3, a0, 4 # number of frames to save in bits 8..4
223 s32i a0, a5, PT_AREG_END - 16
227 addi a0, a4, -1
229 _bnez a0, 1b
281 rsr a0, depc # get a2
283 s32i a0, a2, PT_AREG2
607 2: rotw -1 # a0..a3 become a4..a7
[all …]
Dcoprocessor.S33 jx a0; \
50 jx a0; \
145 rsr a0, cpenable
147 or a0, a0, a2
148 wsr a0, cpenable
153 movi a0, coprocessor_owner # list of owners
154 addx4 a0, a3, a0 # entry for CP
155 l32i a4, a0, 0
171 movi a0, 2f # a0: 'return' address
182 movi a0, coprocessor_owner
[all …]
/arch/riscv/lib/
Duaccess.S26 add t5, a0, a2
35 add t0, a0, a2
49 addi t1, a0, SZREG-1
52 beq a0, t1, .Lskip_align_dst
57 fixup sb a5, 0(a0), 10f
58 addi a0, a0, 1 /* dst */
59 bltu a0, t1, 1b /* t1 - start of aligned dst */
90 fixup REG_S a4, 0(a0), 10f
91 fixup REG_S a5, SZREG(a0), 10f
92 fixup REG_S a6, 2*SZREG(a0), 10f
[all …]
Dtishift.S16 srl a0,a0,a2
19 or a0,a0,a4
24 negw a0,a4
26 srl a0,a1,a0
39 srl a0,a0,a2
42 or a0,a0,a4
47 negw a0,a4
49 sra a0,a1,a0
63 srl a4,a0,a4
64 sll a2,a0,a2
[all …]
/arch/csky/abiv2/
Dstrcmp.S8 mov a3, a0
13 andi t1, a0, 0x3
85 xtrb0 a0, t0
87 subu a0, a2
89 bnez a0, 4f
92 xtrb1 a0, t0
94 subu a0, a2
96 bnez a0, 4f
99 xtrb2 a0, t0
101 subu a0, a2
[all …]
Dmcount.S29 stw a0, (sp, 0)
38 ldw a0, (sp, 0)
69 stw a0, (sp, 0)
76 mov lr, a0
77 ldw a0, (sp, 0)
105 mov a0, lr
106 subi a0, 4
118 lrw a0, ftrace_graph_return
119 ldw a0, (a0, 0)
121 cmpne a0, a1
[all …]
/arch/m68k/kernel/
Dhead.S603 movel %a0@,%a1@
607 movel %a0@,%a1@
611 movel %a0@,%a1@
615 movel %a0@,%a1@
629 movel %a0@,%a1@
633 movel %a0@,%a1@
637 movel %a0@,%a1@
641 movel %a0@,%a1@
645 movel %a0@,%a1@
692 lea %pc@(L(cputype)),%a0
[all …]
/arch/xtensa/boot/boot-elf/
Dbootstrap.S45 movi a0, 0
46 wsr a0, windowbase
48 movi a0, 1
49 wsr a0, windowstart
51 movi a0, 0x1F
52 wsr a0, ps
59 rsil a0, XCHAL_DEBUGLEVEL-1
64 movi a0, CONFIG_KERNEL_LOAD_ADDRESS
66 movi a0, KERNELOFFSET
75 jx a0
/arch/m68k/math-emu/
Dfp_entry.S87 move.l %a0,-(%sp)
228 move.l (PT_OFF_A0+8,%sp),%a0
229 printf PREGISTER,"{a0->%08x}",1,%a0
233 move.l (PT_OFF_A1+8,%sp),%a0
234 printf PREGISTER,"{a1->%08x}",1,%a0
238 move.l (PT_OFF_A2+8,%sp),%a0
239 printf PREGISTER,"{a2->%08x}",1,%a0
243 move.l %a3,%a0
244 printf PREGISTER,"{a3->%08x}",1,%a0
248 move.l %a4,%a0
[all …]
Dfp_util.S95 | %a0 = destination (ptr to struct fp_ext)
98 printf PCONV,"l2e: %p -> %p(",2,%d0,%a0
107 move.l %d1,(%a0)+ | set sign / exp
108 move.l %d0,(%a0)+ | set mantissa
109 clr.l (%a0)
110 subq.l #8,%a0 | restore %a0
111 printx PCONV,%a0@
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
[all …]
Dfp_movem.S143 1: printf PMOVEM,"(%p>%p)",2,%a0,%a1
144 getuser.l (%a0)+,%d2,fp_err_ua1,%a0
149 getuser.l (%a0)+,%d2,fp_err_ua1,%a0
151 getuser.l (%a0),%d2,fp_err_ua1,%a0
153 subq.l #8,%a0
155 add.l %d0,%a0
162 1: printf PMOVEM,"(%p>%p)",2,%a1,%a0
167 putuser.l %d2,(%a0)+,fp_err_ua1,%a0
169 putuser.l %d2,(%a0)+,fp_err_ua1,%a0
171 putuser.l %d2,(%a0),fp_err_ua1,%a0
[all …]
/arch/csky/kernel/
Dentry.S23 mfcr a0, epsr
24 btsti a0, 31
27 ldw a0, (sp, LSAVE_A0)
45 mov a0, sp
82 stw a0, (sp, LSAVE_A0) /* Save return value */
85 mov a0, sp
91 mov a0, sp /* sp = pt_regs pointer */
93 cmpnei a0, 0
96 ldw a0, (sp, LSAVE_A0)
113 stw a0, (sp, LSAVE_A0) /* Save return value */
[all …]
/arch/m68k/coldfire/
Dentry.S67 lea sys_call_table,%a0
69 movel %a0@(%d0),%d3
75 movel %d2,%a0
76 movel %a0@,%a1 /* save top of frame */
78 btst #(TIF_SYSCALL_TRACE%8),%a0@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
81 movel %d3,%a0
82 jbsr %a0@
95 movel %d3,%a0
96 jbsr %a0@
112 movel %d1,%a0
[all …]
/arch/mips/alchemy/common/
Dsleeper.S101 1: lui a0, 0xb400 /* mem_xxx */
102 sw zero, 0x001c(a0) /* Precharge */
104 sw zero, 0x0020(a0) /* Auto Refresh */
106 sw zero, 0x0030(a0) /* Sleep */
127 1: lui a0, 0xb400 /* mem_xxx */
128 sw zero, 0x08c0(a0) /* Precharge */
130 sw zero, 0x08d0(a0) /* Self Refresh */
135 2: lw t1, 0x0850(a0) /* mem_sdstat */
143 lw t1, 0x0840(a0) /* mem_sdconfiga */
145 sw t1, 0x0840(a0) /* mem_sdconfiga */
[all …]
/arch/mips/lib/
Dmemset.S98 andi t0, a0, STORMASK /* aligned? */
121 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
123 EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
125 PTR_SUBU a0, t0 /* long align ptr */
130 EX(sb, a1, N(a0), .Lbyte_fixup\@); \
141 EX(sb, a1, 2(a0), .Lbyte_fixup\@)
147 EX(sb, a1, 6(a0), .Lbyte_fixup\@)
150 ori a0, STORMASK
151 xori a0, STORMASK
152 PTR_ADDIU a0, STORSIZE
[all …]

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