Searched refs:bypass (Results 1 – 25 of 41) sorted by relevance
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/arch/arm/mach-omap2/ |
D | sram.h | 13 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 26 int bypass); 39 int bypass);
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D | clkt2xxx_dpllcore.c | 113 u32 bypass = 0; in omap2_reprogram_dpllcore() local 161 bypass = 1; in omap2_reprogram_dpllcore() 168 bypass); in omap2_reprogram_dpllcore()
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D | sram.c | 159 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 161 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) in omap2_set_prcm() argument 164 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); in omap2_set_prcm()
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D | clkt2xxx_virt_prcm_set.c | 98 u32 cur_rate, done_rate, bypass = 0; in omap2_select_table_rate() local 133 bypass = 1; in omap2_select_table_rate() 151 bypass); in omap2_select_table_rate()
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/arch/mips/cavium-octeon/executive/ |
D | cvmx-helper-jtag.c | 66 jtgc.s.bypass = 0x3; in cvmx_helper_qlm_jtag_init() 68 jtgc.s.bypass = 0xf; in cvmx_helper_qlm_jtag_init()
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/arch/mips/include/asm/octeon/ |
D | cvmx-asxx-defs.h | 200 uint64_t bypass:1; member 202 uint64_t bypass:1; 469 uint64_t bypass:1; member 475 uint64_t bypass:1; 493 uint64_t bypass:1; member 503 uint64_t bypass:1;
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D | cvmx-ciu-defs.h | 121 __BITFIELD_FIELD(uint64_t bypass:4,
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/arch/arm/boot/dts/ |
D | dra72-evm-tps65917.dtsi | 86 regulator-allow-bypass; 93 regulator-allow-bypass;
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D | imx6ul-ccimx6ulsom.dtsi | 264 regulator-allow-bypass; 269 regulator-allow-bypass;
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D | at91-wb50n.dtsi | 46 atmel,osc-bypass;
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D | qcom-pm8941.dtsi | 71 boost_bypass_n_pin: boost-bypass {
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D | dra76-evm.dts | 273 regulator-allow-bypass; 281 regulator-allow-bypass;
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D | am3517.dtsi | 127 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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D | omap34xx.dtsi | 152 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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D | imx27-phytec-phycore-rdk.dts | 316 nxp,no-comparator-bypass;
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D | omap34xx-omap36xx-clocks.dtsi | 170 ti,low-power-bypass;
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D | at91-sama5d27_wlsom1.dtsi | 200 atmel,osc-bypass;
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/arch/arm/mach-omap1/ |
D | sram.S | 36 strh r0, [r2] @ set dpll into bypass mode
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/arch/powerpc/boot/ |
D | 4xx.c | 443 goto bypass; in __ibm440eplike_fixup_clocks() 450 bypass: in __ibm440eplike_fixup_clocks() 771 goto bypass; in ibm405ex_fixup_clocks() 776 bypass: in ibm405ex_fixup_clocks()
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/arch/arm64/boot/dts/qcom/ |
D | msm8992-bullhead-rev-101.dts | 308 pmi8994_bby: boost-bypass {};
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D | msm8992-xiaomi-libra.dts | 406 pmi8994_bby: boost-bypass {
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D | sm8150-mtp.dts | 236 regulator-allow-bypass;
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D | sm8150-hdk.dts | 245 regulator-allow-bypass;
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/arch/sh/kernel/cpu/sh3/ |
D | entry.S | 480 * that isn't a valid hard IRQ, therefore we bypass the do_IRQ()
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/arch/arm/mach-tegra/ |
D | sleep-tegra30.S | 429 bic r1, r1, #(1<<31) @ disable PllP bypass 707 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
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