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Searched refs:cfg (Results 1 – 25 of 173) sorted by relevance

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/arch/x86/pci/
Dmmconfig-shared.c36 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
38 if (cfg->res.parent) in pci_mmconfig_remove()
39 release_resource(&cfg->res); in pci_mmconfig_remove()
40 list_del(&cfg->list); in pci_mmconfig_remove()
41 kfree(cfg); in pci_mmconfig_remove()
46 struct pci_mmcfg_region *cfg, *tmp; in free_all_mmcfg() local
49 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) in free_all_mmcfg()
50 pci_mmconfig_remove(cfg); in free_all_mmcfg()
55 struct pci_mmcfg_region *cfg; in list_add_sorted() local
58 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) { in list_add_sorted()
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Dmmconfig_64.c21 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base() local
23 if (cfg && cfg->virt) in pci_dev_base()
24 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
99 static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg) in mcfg_ioremap() argument
105 start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
106 num_buses = cfg->end_bus - cfg->start_bus + 1; in mcfg_ioremap()
110 addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
116 struct pci_mmcfg_region *cfg; in pci_mmcfg_arch_init() local
118 list_for_each_entry(cfg, &pci_mmcfg_list, list) in pci_mmcfg_arch_init()
119 if (pci_mmcfg_arch_map(cfg)) { in pci_mmcfg_arch_init()
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/arch/arm/mach-s3c/
Dregs-s3c2443-clock.h192 u32 cfg; in s3c_hsudc_init_phy() local
194 cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY; in s3c_hsudc_init_phy()
195 writel(cfg, S3C2443_PWRCFG); in s3c_hsudc_init_phy()
197 cfg = readl(S3C2443_URSTCON); in s3c_hsudc_init_phy()
198 cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); in s3c_hsudc_init_phy()
199 writel(cfg, S3C2443_URSTCON); in s3c_hsudc_init_phy()
202 cfg = readl(S3C2443_URSTCON); in s3c_hsudc_init_phy()
203 cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); in s3c_hsudc_init_phy()
204 writel(cfg, S3C2443_URSTCON); in s3c_hsudc_init_phy()
206 cfg = readl(S3C2443_PHYCTRL); in s3c_hsudc_init_phy()
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Dcpufreq-utils-s3c24xx.c29 void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) in s3c2410_cpufreq_setrefresh() argument
31 struct s3c_cpufreq_board *board = cfg->board; in s3c2410_cpufreq_setrefresh()
42 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
58 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) in s3c2410_set_fvco() argument
60 if (!IS_ERR(cfg->mpll)) in s3c2410_set_fvco()
61 clk_set_rate(cfg->mpll, cfg->pll.frequency); in s3c2410_set_fvco()
Diotiming-s3c2412.c91 static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg, in s3c2412_calc_bank() argument
94 unsigned int hclk = cfg->freq.hclk_tns; in s3c2412_calc_bank()
114 struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_debugfs() argument
138 int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_calc() argument
150 ret = s3c2412_calc_bank(cfg, bt); in s3c2412_iotiming_calc()
171 void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_set() argument
201 static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_getbank() argument
205 unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */ in s3c2412_iotiming_getbank()
228 int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_get() argument
246 s3c2412_iotiming_getbank(cfg, bt, bank); in s3c2412_iotiming_get()
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Diotiming-s3c2410.c213 static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg, in s3c2410_calc_bank() argument
216 unsigned long hclk = cfg->freq.hclk_tns; in s3c2410_calc_bank()
291 static void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg, in s3c2410_iotiming_getbank() argument
295 unsigned long hclk = cfg->freq.hclk_tns; in s3c2410_iotiming_getbank()
311 struct s3c_cpufreq_config *cfg, in s3c2410_iotiming_debugfs() argument
316 unsigned long hclk = cfg->freq.hclk_tns; in s3c2410_iotiming_debugfs()
357 int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, in s3c2410_iotiming_calc() argument
374 ret = s3c2410_calc_bank(cfg, bt); in s3c2410_iotiming_calc()
399 void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, in s3c2410_iotiming_set() argument
431 int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, in s3c2410_iotiming_get() argument
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/arch/arm/mach-davinci/
Dmux.c36 const struct mux_config *cfg; in davinci_cfg_reg() local
56 cfg = &soc_info->pinmux_pins[index]; in davinci_cfg_reg()
58 if (cfg->name == NULL) { in davinci_cfg_reg()
64 if (cfg->mask) { in davinci_cfg_reg()
68 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
70 mask = (cfg->mask << cfg->mask_offset); in davinci_cfg_reg()
74 tmp2 = (cfg->mode << cfg->mask_offset); in davinci_cfg_reg()
80 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
86 pr_warn("initialized %s\n", cfg->name); in davinci_cfg_reg()
91 if (cfg->debug || warn) { in davinci_cfg_reg()
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/arch/mips/loongson64/
Dhpet.c35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
87 int cfg; in hpet_set_state_periodic() local
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/arch/arm/mach-omap2/
Domap-smp.c52 static struct omap_smp_config cfg; variable
71 return cfg.scu_base; in omap4_get_scu_base()
190 cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap4_boot_secondary()
270 cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); in omap4_smp_init_cpus()
271 BUG_ON(!cfg.scu_base); in omap4_smp_init_cpus()
272 ncores = scu_get_core_count(cfg.scu_base); in omap4_smp_init_cpus()
316 released = readl_relaxed(cfg.wakeupgen_base + in omap4_smp_maybe_reset_cpu1()
325 cpu1_startup_pa = readl_relaxed(cfg.wakeupgen_base + in omap4_smp_maybe_reset_cpu1()
372 cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa; in omap4_smp_prepare_cpus()
373 cfg.startup_addr = c->startup_addr; in omap4_smp_prepare_cpus()
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/arch/mips/kernel/
Dcevt-bcm1480.c34 void __iomem *cfg, *init; in sibyte_set_periodic() local
36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
39 __raw_writeq(0, cfg); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
48 void __iomem *cfg; in sibyte_shutdown() local
50 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_shutdown()
53 __raw_writeq(0, cfg); in sibyte_shutdown()
60 void __iomem *cfg, *init; in sibyte_next_event() local
62 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_next_event()
65 __raw_writeq(0, cfg); in sibyte_next_event()
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Dcevt-sb1250.c31 void __iomem *cfg; in sibyte_shutdown() local
33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
36 __raw_writeq(0, cfg); in sibyte_shutdown()
44 void __iomem *cfg, *init; in sibyte_set_periodic() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
51 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
59 void __iomem *cfg, *init; in sibyte_next_event() local
61 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_next_event()
64 __raw_writeq(0, cfg); in sibyte_next_event()
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Dsegment.c16 static void build_segment_config(char *str, unsigned int cfg) in build_segment_config() argument
24 am = (cfg & MIPS_SEGCFG_AM) >> MIPS_SEGCFG_AM_SHIFT; in build_segment_config()
32 if ((am == 0) || (am > 3) || (cfg & MIPS_SEGCFG_EU)) in build_segment_config()
34 ((cfg & MIPS_SEGCFG_PA) >> MIPS_SEGCFG_PA_SHIFT)); in build_segment_config()
40 ((cfg & MIPS_SEGCFG_C) >> MIPS_SEGCFG_C_SHIFT)); in build_segment_config()
46 ((cfg & MIPS_SEGCFG_EU) >> MIPS_SEGCFG_EU_SHIFT)); in build_segment_config()
/arch/arm/mach-omap1/
Dmux.c332 static int omap1_cfg_reg(const struct pin_config *cfg) in omap1_cfg_reg() argument
341 if (cfg->mux_reg) { in omap1_cfg_reg()
345 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
348 mask = (0x7 << cfg->mask_offset); in omap1_cfg_reg()
352 tmp2 = (cfg->mask << cfg->mask_offset); in omap1_cfg_reg()
358 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
364 if (cfg->pu_pd_reg && cfg->pull_val) { in omap1_cfg_reg()
366 pu_pd_orig = omap_readl(cfg->pu_pd_reg); in omap1_cfg_reg()
367 mask = 1 << cfg->pull_bit; in omap1_cfg_reg()
369 if (cfg->pu_pd_val) { in omap1_cfg_reg()
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/arch/arm64/kernel/
Dpci.c71 struct pci_config_window *cfg; /* config space mapping */ member
76 struct pci_config_window *cfg = bus->sysdata; in acpi_pci_bus_find_domain_nr() local
77 struct acpi_device *adev = to_acpi_device(cfg->parent); in acpi_pci_bus_find_domain_nr()
85 struct pci_config_window *cfg; in pcibios_root_bridge_prepare() local
92 cfg = bridge->bus->sysdata; in pcibios_root_bridge_prepare()
99 if (!cfg->parent) in pcibios_root_bridge_prepare()
102 adev = to_acpi_device(cfg->parent); in pcibios_root_bridge_prepare()
138 struct pci_config_window *cfg; in pci_acpi_setup_ecam_mapping() local
155 cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); in pci_acpi_setup_ecam_mapping()
156 if (IS_ERR(cfg)) { in pci_acpi_setup_ecam_mapping()
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/arch/ia64/kernel/
Dirq_ia64.c124 struct irq_cfg *cfg = &irq_cfg[irq]; in __bind_irq_vector() local
132 if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain)) in __bind_irq_vector()
134 if (cfg->vector != IRQ_VECTOR_UNASSIGNED) in __bind_irq_vector()
138 cfg->vector = vector; in __bind_irq_vector()
139 cfg->domain = domain; in __bind_irq_vector()
160 struct irq_cfg *cfg = &irq_cfg[irq]; in __clear_irq_vector() local
163 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED); in __clear_irq_vector()
164 vector = cfg->vector; in __clear_irq_vector()
165 domain = cfg->domain; in __clear_irq_vector()
166 for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask) in __clear_irq_vector()
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/arch/x86/kernel/
Dhpet.c143 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
151 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
153 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
250 u32 cfg = hpet_readl(HPET_CFG); in hpet_stop_counter() local
252 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
253 hpet_writel(cfg, HPET_CFG); in hpet_stop_counter()
264 unsigned int cfg = hpet_readl(HPET_CFG); in hpet_start_counter() local
266 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
267 hpet_writel(cfg, HPET_CFG); in hpet_start_counter()
290 unsigned int cfg = hpet_readl(HPET_CFG); in hpet_enable_legacy_int() local
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Dvsmp_64.c30 unsigned int cap, ctl, cfg; in set_vsmp_ctl() local
33 cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0); in set_vsmp_ctl()
34 address = early_ioremap(cfg, 8); in set_vsmp_ctl()
100 unsigned int cfg, topology, node_shift, maxcpus; in vsmp_cap_cpus() local
111 cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0); in vsmp_cap_cpus()
112 address = early_ioremap(cfg + TOPOLOGY_REGISTER_OFFSET, 4); in vsmp_cap_cpus()
/arch/arm/plat-orion/include/plat/
Daddr-map.h24 int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
28 void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
44 void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
47 void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
52 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
/arch/x86/kernel/apic/
Dmsi.c25 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) in irq_msi_update_msg() argument
29 __irq_msi_compose_msg(cfg, msg, false); in irq_msi_update_msg()
36 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd); in msi_set_affinity() local
43 old_cfg = *cfg; in msi_set_affinity()
65 cfg->vector == old_cfg.vector || in msi_set_affinity()
68 cfg->dest_apicid == old_cfg.dest_apicid) { in msi_set_affinity()
69 irq_msi_update_msg(irqd, cfg); in msi_set_affinity()
78 irq_msi_update_msg(irqd, cfg); in msi_set_affinity()
110 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector]))) in msi_set_affinity()
111 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED); in msi_set_affinity()
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Dipi.c120 unsigned int cfg; in __default_send_IPI_shortcut() local
134 cfg = __prepare_ICR(shortcut, vector, 0); in __default_send_IPI_shortcut()
139 native_apic_mem_write(APIC_ICR, cfg); in __default_send_IPI_shortcut()
148 unsigned long cfg; in __default_send_IPI_dest_field() local
161 cfg = __prepare_ICR2(mask); in __default_send_IPI_dest_field()
162 native_apic_mem_write(APIC_ICR2, cfg); in __default_send_IPI_dest_field()
167 cfg = __prepare_ICR(0, vector, dest); in __default_send_IPI_dest_field()
172 native_apic_mem_write(APIC_ICR, cfg); in __default_send_IPI_dest_field()
/arch/powerpc/platforms/cell/
Dspider-pic.c72 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_unmask_irq() local
74 out_be32(cfg, in_be32(cfg) | 0x30000000u); in spider_unmask_irq()
80 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_mask_irq() local
82 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_mask_irq()
108 void __iomem *cfg = spider_get_irq_config(pic, hw); in spider_set_irq_type() local
142 old_mask = in_be32(cfg) & 0x30000000u; in spider_set_irq_type()
143 out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) | in spider_set_irq_type()
145 out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff)); in spider_set_irq_type()
291 void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i; in spider_init_one() local
292 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_init_one()
/arch/sparc/include/asm/
Dsbi.h97 int cfg; in get_sbi_ctl() local
100 "=r" (cfg) : in get_sbi_ctl()
103 return cfg; in get_sbi_ctl()
106 static inline void set_sbi_ctl(int devid, int cfgno, int cfg) in set_sbi_ctl() argument
109 "r" (cfg), in set_sbi_ctl()
/arch/arc/include/asm/
Dsetup.h33 #define IS_USED_CFG(cfg) IS_USED_RUN(IS_ENABLED(cfg)) argument
34 #define IS_AVAIL2(v, s, cfg) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg)) argument
/arch/mips/netlogic/xlr/
Dfmn-config.c83 struct xlr_board_fmn_config *cfg = &xlr_board_fmn_config; in check_credit_distribution() local
90 total_credits += cfg->cpu[n].credit_config[bkt]; in check_credit_distribution()
91 total_credits += cfg->gmac[0].credit_config[bkt]; in check_credit_distribution()
92 total_credits += cfg->gmac[1].credit_config[bkt]; in check_credit_distribution()
93 total_credits += cfg->dma.credit_config[bkt]; in check_credit_distribution()
94 total_credits += cfg->cmp.credit_config[bkt]; in check_credit_distribution()
95 total_credits += cfg->sae.credit_config[bkt]; in check_credit_distribution()
96 total_credits += cfg->xgmac[0].credit_config[bkt]; in check_credit_distribution()
97 total_credits += cfg->xgmac[1].credit_config[bkt]; in check_credit_distribution()
98 if (total_credits > cfg->bucket_size[bkt]) in check_credit_distribution()
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/arch/x86/kernel/cpu/resctrl/
Dctrlmondata.c63 struct resctrl_staged_config *cfg; in parse_bw() local
67 cfg = &d->staged_config[s->conf_type]; in parse_bw()
68 if (cfg->have_new_ctrl) { in parse_bw()
75 cfg->new_ctrl = bw_val; in parse_bw()
76 cfg->have_new_ctrl = true; in parse_bw()
135 struct resctrl_staged_config *cfg; in parse_cbm() local
139 cfg = &d->staged_config[s->conf_type]; in parse_cbm()
140 if (cfg->have_new_ctrl) { in parse_cbm()
182 cfg->new_ctrl = cbm_val; in parse_cbm()
183 cfg->have_new_ctrl = true; in parse_cbm()
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