1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
4 #ifdef __KERNEL__
5
6 #define ARCH_HAS_IOREMAP_WC
7 #ifdef CONFIG_PPC32
8 #define ARCH_HAS_IOREMAP_WT
9 #endif
10
11 /*
12 */
13
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
18
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
21 /*
22 * has legacy ISA devices ?
23 */
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25 #endif
26
27 #include <linux/device.h>
28 #include <linux/compiler.h>
29 #include <linux/mm.h>
30 #include <asm/page.h>
31 #include <asm/byteorder.h>
32 #include <asm/synch.h>
33 #include <asm/delay.h>
34 #include <asm/mmiowb.h>
35 #include <asm/mmu.h>
36 #include <asm/ppc_asm.h>
37
38 #define SIO_CONFIG_RA 0x398
39 #define SIO_CONFIG_RD 0x399
40
41 #define SLOW_DOWN_IO
42
43 /* 32 bits uses slightly different variables for the various IO
44 * bases. Most of this file only uses _IO_BASE though which we
45 * define properly based on the platform
46 */
47 #ifndef CONFIG_PCI
48 #define _IO_BASE 0
49 #define _ISA_MEM_BASE 0
50 #define PCI_DRAM_OFFSET 0
51 #elif defined(CONFIG_PPC32)
52 #define _IO_BASE isa_io_base
53 #define _ISA_MEM_BASE isa_mem_base
54 #define PCI_DRAM_OFFSET pci_dram_offset
55 #else
56 #define _IO_BASE pci_io_base
57 #define _ISA_MEM_BASE isa_mem_base
58 #define PCI_DRAM_OFFSET 0
59 #endif
60
61 extern unsigned long isa_io_base;
62 extern unsigned long pci_io_base;
63 extern unsigned long pci_dram_offset;
64
65 extern resource_size_t isa_mem_base;
66
67 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
68 * is not set or addresses cannot be translated to MMIO. This is typically
69 * set when the platform supports "special" PIO accesses via a non memory
70 * mapped mechanism, and allows things like the early udbg UART code to
71 * function.
72 */
73 extern bool isa_io_special;
74
75 #ifdef CONFIG_PPC32
76 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
77 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
78 #endif
79 #endif
80
81 /*
82 *
83 * Low level MMIO accessors
84 *
85 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
86 * specific and thus shouldn't be used in generic code. The accessors
87 * provided here are:
88 *
89 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
90 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
91 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
92 *
93 * Those operate directly on a kernel virtual address. Note that the prototype
94 * for the out_* accessors has the arguments in opposite order from the usual
95 * linux PCI accessors. Unlike those, they take the address first and the value
96 * next.
97 *
98 * Note: I might drop the _ns suffix on the stream operations soon as it is
99 * simply normal for stream operations to not swap in the first place.
100 *
101 */
102
103 #define DEF_MMIO_IN_X(name, size, insn) \
104 static inline u##size name(const volatile u##size __iomem *addr) \
105 { \
106 u##size ret; \
107 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
108 : "=r" (ret) : "Z" (*addr) : "memory"); \
109 return ret; \
110 }
111
112 #define DEF_MMIO_OUT_X(name, size, insn) \
113 static inline void name(volatile u##size __iomem *addr, u##size val) \
114 { \
115 __asm__ __volatile__("sync;"#insn" %1,%y0" \
116 : "=Z" (*addr) : "r" (val) : "memory"); \
117 mmiowb_set_pending(); \
118 }
119
120 #define DEF_MMIO_IN_D(name, size, insn) \
121 static inline u##size name(const volatile u##size __iomem *addr) \
122 { \
123 u##size ret; \
124 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
125 : "=r" (ret) : "m"UPD_CONSTR (*addr) : "memory"); \
126 return ret; \
127 }
128
129 #define DEF_MMIO_OUT_D(name, size, insn) \
130 static inline void name(volatile u##size __iomem *addr, u##size val) \
131 { \
132 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
133 : "=m"UPD_CONSTR (*addr) : "r" (val) : "memory"); \
134 mmiowb_set_pending(); \
135 }
136
137 DEF_MMIO_IN_D(in_8, 8, lbz);
138 DEF_MMIO_OUT_D(out_8, 8, stb);
139
140 #ifdef __BIG_ENDIAN__
141 DEF_MMIO_IN_D(in_be16, 16, lhz);
142 DEF_MMIO_IN_D(in_be32, 32, lwz);
143 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
144 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
145
146 DEF_MMIO_OUT_D(out_be16, 16, sth);
147 DEF_MMIO_OUT_D(out_be32, 32, stw);
148 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
149 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
150 #else
151 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
152 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
153 DEF_MMIO_IN_D(in_le16, 16, lhz);
154 DEF_MMIO_IN_D(in_le32, 32, lwz);
155
156 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
157 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
158 DEF_MMIO_OUT_D(out_le16, 16, sth);
159 DEF_MMIO_OUT_D(out_le32, 32, stw);
160
161 #endif /* __BIG_ENDIAN */
162
163 #ifdef __powerpc64__
164
165 #ifdef __BIG_ENDIAN__
166 DEF_MMIO_OUT_D(out_be64, 64, std);
167 DEF_MMIO_IN_D(in_be64, 64, ld);
168
169 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)170 static inline u64 in_le64(const volatile u64 __iomem *addr)
171 {
172 return swab64(in_be64(addr));
173 }
174
out_le64(volatile u64 __iomem * addr,u64 val)175 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
176 {
177 out_be64(addr, swab64(val));
178 }
179 #else
180 DEF_MMIO_OUT_D(out_le64, 64, std);
181 DEF_MMIO_IN_D(in_le64, 64, ld);
182
183 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)184 static inline u64 in_be64(const volatile u64 __iomem *addr)
185 {
186 return swab64(in_le64(addr));
187 }
188
out_be64(volatile u64 __iomem * addr,u64 val)189 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
190 {
191 out_le64(addr, swab64(val));
192 }
193
194 #endif
195 #endif /* __powerpc64__ */
196
197 /*
198 * Low level IO stream instructions are defined out of line for now
199 */
200 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
201 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
202 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
203 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
204 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
205 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
206
207 /* The _ns naming is historical and will be removed. For now, just #define
208 * the non _ns equivalent names
209 */
210 #define _insw _insw_ns
211 #define _insl _insl_ns
212 #define _outsw _outsw_ns
213 #define _outsl _outsl_ns
214
215
216 /*
217 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
218 */
219
220 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
221 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
222 unsigned long n);
223 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
224 unsigned long n);
225
226 /*
227 *
228 * PCI and standard ISA accessors
229 *
230 * Those are globally defined linux accessors for devices on PCI or ISA
231 * busses. They follow the Linux defined semantics. The current implementation
232 * for PowerPC is as close as possible to the x86 version of these, and thus
233 * provides fairly heavy weight barriers for the non-raw versions
234 *
235 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
236 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
237 * own implementation of some or all of the accessors.
238 */
239
240 /*
241 * Include the EEH definitions when EEH is enabled only so they don't get
242 * in the way when building for 32 bits
243 */
244 #ifdef CONFIG_EEH
245 #include <asm/eeh.h>
246 #endif
247
248 /* Shortcut to the MMIO argument pointer */
249 #define PCI_IO_ADDR volatile void __iomem *
250
251 /* Indirect IO address tokens:
252 *
253 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
254 * on all MMIOs. (Note that this is all 64 bits only for now)
255 *
256 * To help platforms who may need to differentiate MMIO addresses in
257 * their hooks, a bitfield is reserved for use by the platform near the
258 * top of MMIO addresses (not PIO, those have to cope the hard way).
259 *
260 * The highest address in the kernel virtual space are:
261 *
262 * d0003fffffffffff # with Hash MMU
263 * c00fffffffffffff # with Radix MMU
264 *
265 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
266 * that can be used for the field.
267 *
268 * The direct IO mapping operations will then mask off those bits
269 * before doing the actual access, though that only happen when
270 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
271 * mechanism
272 *
273 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
274 * all PIO functions call through a hook.
275 */
276
277 #ifdef CONFIG_PPC_INDIRECT_MMIO
278 #define PCI_IO_IND_TOKEN_SHIFT 52
279 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
280 #define PCI_FIX_ADDR(addr) \
281 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
282 #define PCI_GET_ADDR_TOKEN(addr) \
283 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
284 PCI_IO_IND_TOKEN_SHIFT)
285 #define PCI_SET_ADDR_TOKEN(addr, token) \
286 do { \
287 unsigned long __a = (unsigned long)(addr); \
288 __a &= ~PCI_IO_IND_TOKEN_MASK; \
289 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
290 (addr) = (void __iomem *)__a; \
291 } while(0)
292 #else
293 #define PCI_FIX_ADDR(addr) (addr)
294 #endif
295
296
297 /*
298 * Non ordered and non-swapping "raw" accessors
299 */
300
__raw_readb(const volatile void __iomem * addr)301 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
302 {
303 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
304 }
305 #define __raw_readb __raw_readb
306
__raw_readw(const volatile void __iomem * addr)307 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
308 {
309 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
310 }
311 #define __raw_readw __raw_readw
312
__raw_readl(const volatile void __iomem * addr)313 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
314 {
315 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
316 }
317 #define __raw_readl __raw_readl
318
__raw_writeb(unsigned char v,volatile void __iomem * addr)319 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
320 {
321 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
322 }
323 #define __raw_writeb __raw_writeb
324
__raw_writew(unsigned short v,volatile void __iomem * addr)325 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
326 {
327 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
328 }
329 #define __raw_writew __raw_writew
330
__raw_writel(unsigned int v,volatile void __iomem * addr)331 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
332 {
333 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
334 }
335 #define __raw_writel __raw_writel
336
337 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)338 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
339 {
340 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
341 }
342 #define __raw_readq __raw_readq
343
__raw_writeq(unsigned long v,volatile void __iomem * addr)344 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
345 {
346 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
347 }
348 #define __raw_writeq __raw_writeq
349
__raw_writeq_be(unsigned long v,volatile void __iomem * addr)350 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
351 {
352 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
353 }
354 #define __raw_writeq_be __raw_writeq_be
355
356 /*
357 * Real mode versions of the above. Those instructions are only supposed
358 * to be used in hypervisor real mode as per the architecture spec.
359 */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)360 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
361 {
362 __asm__ __volatile__(".machine push; \
363 .machine power6; \
364 stbcix %0,0,%1; \
365 .machine pop;"
366 : : "r" (val), "r" (paddr) : "memory");
367 }
368
__raw_rm_writew(u16 val,volatile void __iomem * paddr)369 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
370 {
371 __asm__ __volatile__(".machine push; \
372 .machine power6; \
373 sthcix %0,0,%1; \
374 .machine pop;"
375 : : "r" (val), "r" (paddr) : "memory");
376 }
377
__raw_rm_writel(u32 val,volatile void __iomem * paddr)378 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
379 {
380 __asm__ __volatile__(".machine push; \
381 .machine power6; \
382 stwcix %0,0,%1; \
383 .machine pop;"
384 : : "r" (val), "r" (paddr) : "memory");
385 }
386
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)387 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
388 {
389 __asm__ __volatile__(".machine push; \
390 .machine power6; \
391 stdcix %0,0,%1; \
392 .machine pop;"
393 : : "r" (val), "r" (paddr) : "memory");
394 }
395
__raw_rm_writeq_be(u64 val,volatile void __iomem * paddr)396 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
397 {
398 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
399 }
400
__raw_rm_readb(volatile void __iomem * paddr)401 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
402 {
403 u8 ret;
404 __asm__ __volatile__(".machine push; \
405 .machine power6; \
406 lbzcix %0,0, %1; \
407 .machine pop;"
408 : "=r" (ret) : "r" (paddr) : "memory");
409 return ret;
410 }
411
__raw_rm_readw(volatile void __iomem * paddr)412 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
413 {
414 u16 ret;
415 __asm__ __volatile__(".machine push; \
416 .machine power6; \
417 lhzcix %0,0, %1; \
418 .machine pop;"
419 : "=r" (ret) : "r" (paddr) : "memory");
420 return ret;
421 }
422
__raw_rm_readl(volatile void __iomem * paddr)423 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
424 {
425 u32 ret;
426 __asm__ __volatile__(".machine push; \
427 .machine power6; \
428 lwzcix %0,0, %1; \
429 .machine pop;"
430 : "=r" (ret) : "r" (paddr) : "memory");
431 return ret;
432 }
433
__raw_rm_readq(volatile void __iomem * paddr)434 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
435 {
436 u64 ret;
437 __asm__ __volatile__(".machine push; \
438 .machine power6; \
439 ldcix %0,0, %1; \
440 .machine pop;"
441 : "=r" (ret) : "r" (paddr) : "memory");
442 return ret;
443 }
444 #endif /* __powerpc64__ */
445
446 /*
447 *
448 * PCI PIO and MMIO accessors.
449 *
450 *
451 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
452 * machine checks (which they occasionally do when probing non existing
453 * IO ports on some platforms, like PowerMac and 8xx).
454 * I always found it to be of dubious reliability and I am tempted to get
455 * rid of it one of these days. So if you think it's important to keep it,
456 * please voice up asap. We never had it for 64 bits and I do not intend
457 * to port it over
458 */
459
460 #ifdef CONFIG_PPC32
461
462 #define __do_in_asm(name, op) \
463 static inline unsigned int name(unsigned int port) \
464 { \
465 unsigned int x; \
466 __asm__ __volatile__( \
467 "sync\n" \
468 "0:" op " %0,0,%1\n" \
469 "1: twi 0,%0,0\n" \
470 "2: isync\n" \
471 "3: nop\n" \
472 "4:\n" \
473 ".section .fixup,\"ax\"\n" \
474 "5: li %0,-1\n" \
475 " b 4b\n" \
476 ".previous\n" \
477 EX_TABLE(0b, 5b) \
478 EX_TABLE(1b, 5b) \
479 EX_TABLE(2b, 5b) \
480 EX_TABLE(3b, 5b) \
481 : "=&r" (x) \
482 : "r" (port + _IO_BASE) \
483 : "memory"); \
484 return x; \
485 }
486
487 #define __do_out_asm(name, op) \
488 static inline void name(unsigned int val, unsigned int port) \
489 { \
490 __asm__ __volatile__( \
491 "sync\n" \
492 "0:" op " %0,0,%1\n" \
493 "1: sync\n" \
494 "2:\n" \
495 EX_TABLE(0b, 2b) \
496 EX_TABLE(1b, 2b) \
497 : : "r" (val), "r" (port + _IO_BASE) \
498 : "memory"); \
499 }
500
501 __do_in_asm(_rec_inb, "lbzx")
502 __do_in_asm(_rec_inw, "lhbrx")
503 __do_in_asm(_rec_inl, "lwbrx")
504 __do_out_asm(_rec_outb, "stbx")
505 __do_out_asm(_rec_outw, "sthbrx")
506 __do_out_asm(_rec_outl, "stwbrx")
507
508 #endif /* CONFIG_PPC32 */
509
510 /* The "__do_*" operations below provide the actual "base" implementation
511 * for each of the defined accessors. Some of them use the out_* functions
512 * directly, some of them still use EEH, though we might change that in the
513 * future. Those macros below provide the necessary argument swapping and
514 * handling of the IO base for PIO.
515 *
516 * They are themselves used by the macros that define the actual accessors
517 * and can be used by the hooks if any.
518 *
519 * Note that PIO operations are always defined in terms of their corresonding
520 * MMIO operations. That allows platforms like iSeries who want to modify the
521 * behaviour of both to only hook on the MMIO version and get both. It's also
522 * possible to hook directly at the toplevel PIO operation if they have to
523 * be handled differently
524 */
525 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
526 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
527 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
528 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
529 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
530 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
531 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
532
533 #ifdef CONFIG_EEH
534 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
535 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
536 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
537 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
538 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
539 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
540 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
541 #else /* CONFIG_EEH */
542 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
543 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
544 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
545 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
546 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
547 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
548 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
549 #endif /* !defined(CONFIG_EEH) */
550
551 #ifdef CONFIG_PPC32
552 #define __do_outb(val, port) _rec_outb(val, port)
553 #define __do_outw(val, port) _rec_outw(val, port)
554 #define __do_outl(val, port) _rec_outl(val, port)
555 #define __do_inb(port) _rec_inb(port)
556 #define __do_inw(port) _rec_inw(port)
557 #define __do_inl(port) _rec_inl(port)
558 #else /* CONFIG_PPC32 */
559 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
560 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
561 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
562 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
563 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
564 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
565 #endif /* !CONFIG_PPC32 */
566
567 #ifdef CONFIG_EEH
568 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
569 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
570 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
571 #else /* CONFIG_EEH */
572 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
573 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
574 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
575 #endif /* !CONFIG_EEH */
576 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
577 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
578 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
579
580 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
581 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
582 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
583 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
584 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
585 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
586
587 #define __do_memset_io(addr, c, n) \
588 _memset_io(PCI_FIX_ADDR(addr), c, n)
589 #define __do_memcpy_toio(dst, src, n) \
590 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
591
592 #ifdef CONFIG_EEH
593 #define __do_memcpy_fromio(dst, src, n) \
594 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
595 #else /* CONFIG_EEH */
596 #define __do_memcpy_fromio(dst, src, n) \
597 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
598 #endif /* !CONFIG_EEH */
599
600 #ifdef CONFIG_PPC_INDIRECT_PIO
601 #define DEF_PCI_HOOK_pio(x) x
602 #else
603 #define DEF_PCI_HOOK_pio(x) NULL
604 #endif
605
606 #ifdef CONFIG_PPC_INDIRECT_MMIO
607 #define DEF_PCI_HOOK_mem(x) x
608 #else
609 #define DEF_PCI_HOOK_mem(x) NULL
610 #endif
611
612 /* Structure containing all the hooks */
613 extern struct ppc_pci_io {
614
615 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
616 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
617
618 #include <asm/io-defs.h>
619
620 #undef DEF_PCI_AC_RET
621 #undef DEF_PCI_AC_NORET
622
623 } ppc_pci_io;
624
625 /* The inline wrappers */
626 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
627 static inline ret name at \
628 { \
629 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
630 return ppc_pci_io.name al; \
631 return __do_##name al; \
632 }
633
634 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
635 static inline void name at \
636 { \
637 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
638 ppc_pci_io.name al; \
639 else \
640 __do_##name al; \
641 }
642
643 #include <asm/io-defs.h>
644
645 #undef DEF_PCI_AC_RET
646 #undef DEF_PCI_AC_NORET
647
648 /* Some drivers check for the presence of readq & writeq with
649 * a #ifdef, so we make them happy here.
650 */
651 #define readb readb
652 #define readw readw
653 #define readl readl
654 #define writeb writeb
655 #define writew writew
656 #define writel writel
657 #define readsb readsb
658 #define readsw readsw
659 #define readsl readsl
660 #define writesb writesb
661 #define writesw writesw
662 #define writesl writesl
663 #define inb inb
664 #define inw inw
665 #define inl inl
666 #define outb outb
667 #define outw outw
668 #define outl outl
669 #define insb insb
670 #define insw insw
671 #define insl insl
672 #define outsb outsb
673 #define outsw outsw
674 #define outsl outsl
675 #ifdef __powerpc64__
676 #define readq readq
677 #define writeq writeq
678 #endif
679 #define memset_io memset_io
680 #define memcpy_fromio memcpy_fromio
681 #define memcpy_toio memcpy_toio
682
683 /*
684 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
685 * access
686 */
687 #define xlate_dev_mem_ptr(p) __va(p)
688
689 /*
690 * We don't do relaxed operations yet, at least not with this semantic
691 */
692 #define readb_relaxed(addr) readb(addr)
693 #define readw_relaxed(addr) readw(addr)
694 #define readl_relaxed(addr) readl(addr)
695 #define readq_relaxed(addr) readq(addr)
696 #define writeb_relaxed(v, addr) writeb(v, addr)
697 #define writew_relaxed(v, addr) writew(v, addr)
698 #define writel_relaxed(v, addr) writel(v, addr)
699 #define writeq_relaxed(v, addr) writeq(v, addr)
700
701 #ifdef CONFIG_GENERIC_IOMAP
702 #include <asm-generic/iomap.h>
703 #else
704 /*
705 * Here comes the implementation of the IOMAP interfaces.
706 */
ioread16be(const void __iomem * addr)707 static inline unsigned int ioread16be(const void __iomem *addr)
708 {
709 return readw_be(addr);
710 }
711 #define ioread16be ioread16be
712
ioread32be(const void __iomem * addr)713 static inline unsigned int ioread32be(const void __iomem *addr)
714 {
715 return readl_be(addr);
716 }
717 #define ioread32be ioread32be
718
719 #ifdef __powerpc64__
ioread64_lo_hi(const void __iomem * addr)720 static inline u64 ioread64_lo_hi(const void __iomem *addr)
721 {
722 return readq(addr);
723 }
724 #define ioread64_lo_hi ioread64_lo_hi
725
ioread64_hi_lo(const void __iomem * addr)726 static inline u64 ioread64_hi_lo(const void __iomem *addr)
727 {
728 return readq(addr);
729 }
730 #define ioread64_hi_lo ioread64_hi_lo
731
ioread64be(const void __iomem * addr)732 static inline u64 ioread64be(const void __iomem *addr)
733 {
734 return readq_be(addr);
735 }
736 #define ioread64be ioread64be
737
ioread64be_lo_hi(const void __iomem * addr)738 static inline u64 ioread64be_lo_hi(const void __iomem *addr)
739 {
740 return readq_be(addr);
741 }
742 #define ioread64be_lo_hi ioread64be_lo_hi
743
ioread64be_hi_lo(const void __iomem * addr)744 static inline u64 ioread64be_hi_lo(const void __iomem *addr)
745 {
746 return readq_be(addr);
747 }
748 #define ioread64be_hi_lo ioread64be_hi_lo
749 #endif /* __powerpc64__ */
750
iowrite16be(u16 val,void __iomem * addr)751 static inline void iowrite16be(u16 val, void __iomem *addr)
752 {
753 writew_be(val, addr);
754 }
755 #define iowrite16be iowrite16be
756
iowrite32be(u32 val,void __iomem * addr)757 static inline void iowrite32be(u32 val, void __iomem *addr)
758 {
759 writel_be(val, addr);
760 }
761 #define iowrite32be iowrite32be
762
763 #ifdef __powerpc64__
iowrite64_lo_hi(u64 val,void __iomem * addr)764 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
765 {
766 writeq(val, addr);
767 }
768 #define iowrite64_lo_hi iowrite64_lo_hi
769
iowrite64_hi_lo(u64 val,void __iomem * addr)770 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
771 {
772 writeq(val, addr);
773 }
774 #define iowrite64_hi_lo iowrite64_hi_lo
775
iowrite64be(u64 val,void __iomem * addr)776 static inline void iowrite64be(u64 val, void __iomem *addr)
777 {
778 writeq_be(val, addr);
779 }
780 #define iowrite64be iowrite64be
781
iowrite64be_lo_hi(u64 val,void __iomem * addr)782 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
783 {
784 writeq_be(val, addr);
785 }
786 #define iowrite64be_lo_hi iowrite64be_lo_hi
787
iowrite64be_hi_lo(u64 val,void __iomem * addr)788 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
789 {
790 writeq_be(val, addr);
791 }
792 #define iowrite64be_hi_lo iowrite64be_hi_lo
793 #endif /* __powerpc64__ */
794
795 struct pci_dev;
796 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
797 #define pci_iounmap pci_iounmap
798 void __iomem *ioport_map(unsigned long port, unsigned int len);
799 #define ioport_map ioport_map
800 #endif
801
iosync(void)802 static inline void iosync(void)
803 {
804 __asm__ __volatile__ ("sync" : : : "memory");
805 }
806
807 /* Enforce in-order execution of data I/O.
808 * No distinction between read/write on PPC; use eieio for all three.
809 * Those are fairly week though. They don't provide a barrier between
810 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
811 * they only provide barriers between 2 __raw MMIO operations and
812 * possibly break write combining.
813 */
814 #define iobarrier_rw() eieio()
815 #define iobarrier_r() eieio()
816 #define iobarrier_w() eieio()
817
818
819 /*
820 * output pause versions need a delay at least for the
821 * w83c105 ide controller in a p610.
822 */
823 #define inb_p(port) inb(port)
824 #define outb_p(val, port) (udelay(1), outb((val), (port)))
825 #define inw_p(port) inw(port)
826 #define outw_p(val, port) (udelay(1), outw((val), (port)))
827 #define inl_p(port) inl(port)
828 #define outl_p(val, port) (udelay(1), outl((val), (port)))
829
830
831 #define IO_SPACE_LIMIT ~(0UL)
832
833 /**
834 * ioremap - map bus memory into CPU space
835 * @address: bus address of the memory
836 * @size: size of the resource to map
837 *
838 * ioremap performs a platform specific sequence of operations to
839 * make bus memory CPU accessible via the readb/readw/readl/writeb/
840 * writew/writel functions and the other mmio helpers. The returned
841 * address is not guaranteed to be usable directly as a virtual
842 * address.
843 *
844 * We provide a few variations of it:
845 *
846 * * ioremap is the standard one and provides non-cacheable guarded mappings
847 * and can be hooked by the platform via ppc_md
848 *
849 * * ioremap_prot allows to specify the page flags as an argument and can
850 * also be hooked by the platform via ppc_md.
851 *
852 * * ioremap_wc enables write combining
853 *
854 * * ioremap_wt enables write through
855 *
856 * * ioremap_coherent maps coherent cached memory
857 *
858 * * iounmap undoes such a mapping and can be hooked
859 *
860 * * __ioremap_caller is the same as above but takes an explicit caller
861 * reference rather than using __builtin_return_address(0)
862 *
863 */
864 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
865 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
866 unsigned long flags);
867 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
868 #define ioremap_wc ioremap_wc
869
870 #ifdef CONFIG_PPC32
871 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
872 #define ioremap_wt ioremap_wt
873 #endif
874
875 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
876 #define ioremap_uc(addr, size) ioremap((addr), (size))
877 #define ioremap_cache(addr, size) \
878 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
879
880 extern void iounmap(volatile void __iomem *addr);
881
882 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
883
884 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
885 unsigned long size, pgprot_t prot);
886 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
887 pgprot_t prot, void *caller);
888
889 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
890 pgprot_t prot, void *caller);
891
892 /*
893 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
894 * which needs some additional definitions here. They basically allow PIO
895 * space overall to be 1GB. This will work as long as we never try to use
896 * iomap to map MMIO below 1GB which should be fine on ppc64
897 */
898 #define HAVE_ARCH_PIO_SIZE 1
899 #define PIO_OFFSET 0x00000000UL
900 #define PIO_MASK (FULL_IO_SIZE - 1)
901 #define PIO_RESERVED (FULL_IO_SIZE)
902
903 #define mmio_read16be(addr) readw_be(addr)
904 #define mmio_read32be(addr) readl_be(addr)
905 #define mmio_read64be(addr) readq_be(addr)
906 #define mmio_write16be(val, addr) writew_be(val, addr)
907 #define mmio_write32be(val, addr) writel_be(val, addr)
908 #define mmio_write64be(val, addr) writeq_be(val, addr)
909 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
910 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
911 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
912 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
913 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
914 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
915
916 /**
917 * virt_to_phys - map virtual addresses to physical
918 * @address: address to remap
919 *
920 * The returned physical address is the physical (CPU) mapping for
921 * the memory address given. It is only valid to use this function on
922 * addresses directly mapped or allocated via kmalloc.
923 *
924 * This function does not give bus mappings for DMA transfers. In
925 * almost all conceivable cases a device driver should not be using
926 * this function
927 */
virt_to_phys(volatile void * address)928 static inline unsigned long virt_to_phys(volatile void * address)
929 {
930 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
931
932 return __pa((unsigned long)address);
933 }
934 #define virt_to_phys virt_to_phys
935
936 /**
937 * phys_to_virt - map physical address to virtual
938 * @address: address to remap
939 *
940 * The returned virtual address is a current CPU mapping for
941 * the memory address given. It is only valid to use this function on
942 * addresses that have a kernel mapping
943 *
944 * This function does not handle bus mappings for DMA transfers. In
945 * almost all conceivable cases a device driver should not be using
946 * this function
947 */
phys_to_virt(unsigned long address)948 static inline void * phys_to_virt(unsigned long address)
949 {
950 return (void *)__va(address);
951 }
952 #define phys_to_virt phys_to_virt
953
954 /*
955 * Change "struct page" to physical address.
956 */
page_to_phys(struct page * page)957 static inline phys_addr_t page_to_phys(struct page *page)
958 {
959 unsigned long pfn = page_to_pfn(page);
960
961 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
962
963 return PFN_PHYS(pfn);
964 }
965
966 /*
967 * 32 bits still uses virt_to_bus() for it's implementation of DMA
968 * mappings se we have to keep it defined here. We also have some old
969 * drivers (shame shame shame) that use bus_to_virt() and haven't been
970 * fixed yet so I need to define it here.
971 */
972 #ifdef CONFIG_PPC32
973
virt_to_bus(volatile void * address)974 static inline unsigned long virt_to_bus(volatile void * address)
975 {
976 if (address == NULL)
977 return 0;
978 return __pa(address) + PCI_DRAM_OFFSET;
979 }
980 #define virt_to_bus virt_to_bus
981
bus_to_virt(unsigned long address)982 static inline void * bus_to_virt(unsigned long address)
983 {
984 if (address == 0)
985 return NULL;
986 return __va(address - PCI_DRAM_OFFSET);
987 }
988 #define bus_to_virt bus_to_virt
989
990 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
991
992 #endif /* CONFIG_PPC32 */
993
994 /* access ports */
995 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
996 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
997
998 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
999 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
1000
1001 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
1002 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
1003
1004 /* Clear and set bits in one shot. These macros can be used to clear and
1005 * set multiple bits in a register using a single read-modify-write. These
1006 * macros can also be used to set a multiple-bit bit pattern using a mask,
1007 * by specifying the mask in the 'clear' parameter and the new bit pattern
1008 * in the 'set' parameter.
1009 */
1010
1011 #define clrsetbits(type, addr, clear, set) \
1012 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
1013
1014 #ifdef __powerpc64__
1015 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
1016 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
1017 #endif
1018
1019 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
1020 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
1021
1022 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
1023 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1024
1025 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1026
1027 #include <asm-generic/io.h>
1028
1029 #endif /* __KERNEL__ */
1030
1031 #endif /* _ASM_POWERPC_IO_H */
1032