| /arch/arm64/kvm/hyp/ |
| D | aarch32.c | 49 unsigned long cpsr; in kvm_condition_valid32() local
62 cpsr = *vcpu_cpsr(vcpu); in kvm_condition_valid32()
68 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); in kvm_condition_valid32()
78 cpsr_cond = cpsr >> 28; in kvm_condition_valid32()
99 unsigned long cpsr = *vcpu_cpsr(vcpu); in kvm_adjust_itstate() local
100 bool is_arm = !(cpsr & PSR_AA32_T_BIT); in kvm_adjust_itstate()
102 if (is_arm || !(cpsr & PSR_AA32_IT_MASK)) in kvm_adjust_itstate()
105 cond = (cpsr & 0xe000) >> 13; in kvm_adjust_itstate()
106 itbits = (cpsr & 0x1c00) >> (10 - 2); in kvm_adjust_itstate()
107 itbits |= (cpsr & (0x3 << 25)) >> 25; in kvm_adjust_itstate()
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| /arch/arm/probes/ |
| D | decode.c | 84 static unsigned long __kprobes __check_eq(unsigned long cpsr) in __check_eq() argument
86 return cpsr & PSR_Z_BIT; in __check_eq()
89 static unsigned long __kprobes __check_ne(unsigned long cpsr) in __check_ne() argument
91 return (~cpsr) & PSR_Z_BIT; in __check_ne()
94 static unsigned long __kprobes __check_cs(unsigned long cpsr) in __check_cs() argument
96 return cpsr & PSR_C_BIT; in __check_cs()
99 static unsigned long __kprobes __check_cc(unsigned long cpsr) in __check_cc() argument
101 return (~cpsr) & PSR_C_BIT; in __check_cc()
104 static unsigned long __kprobes __check_mi(unsigned long cpsr) in __check_mi() argument
106 return cpsr & PSR_N_BIT; in __check_mi()
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| D | decode-thumb.h | 17 #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000) argument
24 #define current_cond(cpsr) ((cpsr >> 12) & 0xf) argument
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| D | decode.h | 41 long cpsr = regs->ARM_cpsr; in bx_write_pc() local
43 cpsr |= PSR_T_BIT; in bx_write_pc()
46 cpsr &= ~PSR_T_BIT; in bx_write_pc()
49 regs->ARM_cpsr = cpsr; in bx_write_pc()
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| D | decode-thumb.c | 836 static unsigned long __kprobes thumb_check_cc(unsigned long cpsr) in thumb_check_cc() argument
838 if (unlikely(in_it_block(cpsr))) in thumb_check_cc()
839 return probes_condition_checks[current_cond(cpsr)](cpsr); in thumb_check_cc()
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| /arch/arm/probes/kprobes/ |
| D | actions-arm.c | 170 unsigned long cpsr = regs->ARM_cpsr; in emulate_rd12rn16rm0rs8_rwflags() local
176 : "=r" (rdv), [cpsr] "=r" (cpsr) in emulate_rd12rn16rm0rs8_rwflags()
178 "1" (cpsr), [fn] "r" (asi->insn_fn) in emulate_rd12rn16rm0rs8_rwflags()
186 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); in emulate_rd12rn16rm0rs8_rwflags()
200 unsigned long cpsr = regs->ARM_cpsr; in emulate_rd12rn16rm0_rwflags_nopc() local
206 : "=r" (rdv), [cpsr] "=r" (cpsr) in emulate_rd12rn16rm0_rwflags_nopc()
208 "1" (cpsr), [fn] "r" (asi->insn_fn) in emulate_rd12rn16rm0_rwflags_nopc()
213 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); in emulate_rd12rn16rm0_rwflags_nopc()
230 unsigned long cpsr = regs->ARM_cpsr; in emulate_rd16rn12rm0rs8_rwflags_nopc() local
236 : "=r" (rdv), [cpsr] "=r" (cpsr) in emulate_rd16rn12rm0rs8_rwflags_nopc()
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| D | actions-thumb.c | 221 unsigned long cpsr = regs->ARM_cpsr; in t32_emulate_rd8rn16rm0_rwflags() local
227 : "=r" (rdv), [cpsr] "=r" (cpsr) in t32_emulate_rd8rn16rm0_rwflags()
229 "1" (cpsr), [fn] "r" (asi->insn_fn) in t32_emulate_rd8rn16rm0_rwflags()
234 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK); in t32_emulate_rd8rn16rm0_rwflags()
388 unsigned long cpsr = regs->ARM_cpsr; in t16_simulate_it() local
389 cpsr &= ~PSR_IT_MASK; in t16_simulate_it()
390 cpsr |= (insn & 0xfc) << 8; in t16_simulate_it()
391 cpsr |= (insn & 0x03) << 25; in t16_simulate_it()
392 regs->ARM_cpsr = cpsr; in t16_simulate_it()
475 unsigned long cpsr = t16_emulate_loregs(insn, asi, regs); in t16_emulate_loregs_noitrwflags() local
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| D | test-core.c | 1010 static unsigned long test_check_cc(int cc, unsigned long cpsr) in test_check_cc() argument
1012 int ret = arm_check_condition(cc << 28, cpsr); in test_check_cc()
1023 unsigned long cpsr; in test_context_cpsr() local
1028 cpsr = (scenario & 0xf) << 28; /* N,Z,C,V flags */ in test_context_cpsr()
1029 cpsr |= (scenario & 0xf) << 16; /* GE flags */ in test_context_cpsr()
1030 cpsr |= (scenario & 0x1) << 27; /* Toggle Q flag */ in test_context_cpsr()
1036 probe_should_run = test_check_cc(cc, cpsr) != 0; in test_context_cpsr()
1044 probe_should_run = test_check_cc(cc, cpsr) != 0; in test_context_cpsr()
1064 cpsr |= cond_base << 13; /* ITSTATE<7:5> */ in test_context_cpsr()
1065 cpsr |= (mask & 0x1) << 12; /* ITSTATE<4> */ in test_context_cpsr()
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| /arch/arm/include/asm/ |
| D | ptrace.h | 174 static inline unsigned long it_advance(unsigned long cpsr) in it_advance() argument
176 if ((cpsr & 0x06000400) == 0) { in it_advance()
178 cpsr &= ~PSR_IT_MASK; in it_advance()
182 unsigned long it = cpsr & mask; in it_advance()
186 cpsr &= ~mask; in it_advance()
187 cpsr |= it; in it_advance()
189 return cpsr; in it_advance()
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| D | assembler.h | 165 mrs \oldcpsr, cpsr
174 mrs \oldcpsr, cpsr
373 mrs \reg , cpsr
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| /arch/arm64/kvm/ |
| D | trace_arm.h | 119 unsigned long cpsr),
120 TP_ARGS(vcpu_pc, instr, cpsr),
125 __field( unsigned long, cpsr )
131 __entry->cpsr = cpsr;
135 __entry->vcpu_pc, __entry->instr, __entry->cpsr)
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| D | inject_fault.c | 19 unsigned long cpsr = *vcpu_cpsr(vcpu); in inject_abt64() local
40 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t) in inject_abt64()
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| /arch/arm/kernel/ |
| D | fiqasm.S | 27 mrs r1, cpsr
40 mrs r1, cpsr
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| D | signal.c | 327 unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT); in setup_return() local
339 cpsr |= PSR_ENDSTATE; in setup_return()
345 cpsr = (cpsr & ~MODE_MASK) | USR_MODE; in setup_return()
366 cpsr &= ~PSR_IT_MASK; in setup_return()
369 cpsr |= PSR_T_BIT; in setup_return()
371 cpsr &= ~PSR_T_BIT; in setup_return()
410 if (cpsr & MODE32_BIT) { in setup_return()
440 regs->ARM_cpsr = cpsr; in setup_return()
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| D | hyp-stub.S | 30 mrs \reg1, cpsr
80 mrs r4, cpsr
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| D | entry-header.S | 179 mrs \rtemp, cpsr
191 mrs \rtemp, cpsr
330 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
346 movs pc, lr @ return & move spsr_svc into cpsr
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| D | iwmmxt.S | 197 mrs ip, cpsr
249 mrs ip, cpsr
287 mrs ip, cpsr
354 mrs r2, cpsr
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| D | entry-armv.S | 264 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
1013 mrs r0, cpsr
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| D | ptrace.c | 86 REG_OFFSET_NAME(cpsr),
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| /arch/arm/mach-rpc/ |
| D | ecard-loader.S | 13 mrs rt, cpsr; \
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| /arch/arm/mm/ |
| D | proc-feroceon.S | 248 mrs r2, cpsr
289 mrs r2, cpsr
325 mrs r2, cpsr
356 mrs r2, cpsr
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| D | cache-v6.S | 38 mrs r1, cpsr
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| D | proc-arm926.S | 93 mrs r3, cpsr @ Disable FIQs while Icache
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| /arch/arm64/kvm/hyp/nvhe/ |
| D | hyp-main.c | 160 unsigned long cpsr = *vcpu_cpsr(shadow_vcpu); in handle_pvm_entry_iabt() local
173 if ((cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t) in handle_pvm_entry_iabt()
200 unsigned long cpsr = *vcpu_cpsr(shadow_vcpu); in handle_pvm_entry_dabt() local
203 if ((cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t) in handle_pvm_entry_dabt()
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| /arch/arm/boot/compressed/ |
| D | head.S | 229 AR_CLASS( mrs r9, cpsr )
242 mrs r2, cpsr @ get current mode
1474 mrs r0, cpsr @ get the current mode
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