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Searched refs:crg (Results 1 – 4 of 4) sorted by relevance

/arch/arm64/boot/dts/hisilicon/
Dhi3798cv200.dtsi85 crg: clock-reset-controller@8a22000 { label
86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
119 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
120 resets = <&crg 0xbc 4>;
127 resets = <&crg 0xbc 8>;
133 resets = <&crg 0xbc 9>;
140 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
141 resets = <&crg 0xbc 6>;
148 resets = <&crg 0xbc 10>;
156 clocks = <&crg HISTB_COMBPHY0_CLK>;
[all …]
Dhi3670.dtsi186 compatible = "hisilicon,hi3670-media1-crg", "syscon";
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
/arch/arm/boot/dts/
Dhi3519.dtsi37 crg: clock-reset-controller@12010000 { label
38 compatible = "hisilicon,hi3519-crg";
55 clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
64 clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
73 clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
82 clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
91 clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
130 clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
142 clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
154 clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
/arch/x86/kernel/cpu/resctrl/
Drdtgroup.c811 struct rdtgroup *crg; in proc_resctrl_show() local
827 list_for_each_entry(crg, &rdtg->mon.crdtgrp_list, in proc_resctrl_show()
829 if (tsk->rmid != crg->mon.rmid) in proc_resctrl_show()
831 seq_printf(s, "%s", crg->kn->name); in proc_resctrl_show()