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Searched refs:ctrl_base (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-hisi/
Dhotplug.c73 static void __iomem *ctrl_base; variable
84 ctrl_base + SCPERPWREN); in set_cpu_hi3620()
88 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
101 ctrl_base + SCISODIS); in set_cpu_hi3620()
105 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
107 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
112 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
115 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
[all …]
Dplatsmp.c21 static void __iomem *ctrl_base; variable
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
62 if (!ctrl_base) { in hi3xxx_smp_prepare_cpus()
68 ctrl_base = of_iomap(np, 0); in hi3xxx_smp_prepare_cpus()
69 if (!ctrl_base) { in hi3xxx_smp_prepare_cpus()
79 ctrl_base += offset; in hi3xxx_smp_prepare_cpus()
165 ctrl_base = of_iomap(node, 0); in hip01_boot_secondary()
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/arch/arm/mach-omap2/
Domap_phy_internal.c36 void __iomem *ctrl_base; in omap4430_phy_power_down() local
41 ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); in omap4430_phy_power_down()
42 if (!ctrl_base) { in omap4430_phy_power_down()
48 writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF); in omap4430_phy_power_down()
50 iounmap(ctrl_base); in omap4430_phy_power_down()
/arch/mips/pci/
Dpci-ar724x.c41 void __iomem *ctrl_base; member
60 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
236 base = apc->ctrl_base; in ar724x_pci_irq_handler()
256 base = apc->ctrl_base; in ar724x_pci_irq_unmask()
277 base = apc->ctrl_base; in ar724x_pci_irq_mask()
311 base = apc->ctrl_base; in ar724x_pci_irq_init()
349 app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); in ar724x_pci_hw_init()
351 __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP); in ar724x_pci_hw_init()
375 apc->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl_base"); in ar724x_pci_probe()
376 if (IS_ERR(apc->ctrl_base)) in ar724x_pci_probe()
[all …]
/arch/arm/mm/
Dcache-uniphier.c73 void __iomem *ctrl_base; member
224 writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC); in __uniphier_cache_enable()
374 data->ctrl_base = of_iomap(np, 0); in __uniphier_cache_init()
375 if (!data->ctrl_base) { in __uniphier_cache_init()
395 data->way_ctrl_base = data->ctrl_base + 0xc00; in __uniphier_cache_init()
412 data->way_ctrl_base = data->ctrl_base + 0x870; in __uniphier_cache_init()
416 data->way_ctrl_base = data->ctrl_base + 0x840; in __uniphier_cache_init()
445 iounmap(data->ctrl_base); in __uniphier_cache_init()
/arch/arm/kernel/
Dhw_breakpoint.c329 int i, max_slots, ctrl_base, val_base; in arch_install_hw_breakpoint() local
337 ctrl_base = ARM_BASE_BCR; in arch_install_hw_breakpoint()
343 ctrl_base = ARM_BASE_WCR; in arch_install_hw_breakpoint()
369 ctrl_base = ARM_BASE_BCR + core_num_brps; in arch_install_hw_breakpoint()
378 write_wb_reg(ctrl_base + i, ctrl); in arch_install_hw_breakpoint()