| /arch/x86/lib/ |
| D | insn.c | 37 #define validate_next(t, insn, n) \ argument
38 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
40 #define __get_next(t, insn) \ argument
41 …({ t r = get_unaligned((t *)(insn)->next_byte); (insn)->next_byte += sizeof(t); leXX_to_cpu(t, r);…
43 #define __peek_nbyte_next(t, insn, n) \ argument
44 ({ t r = get_unaligned((t *)(insn)->next_byte + n); leXX_to_cpu(t, r); })
46 #define get_next(t, insn) \ argument
47 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
49 #define peek_nbyte_next(t, insn, n) \ argument
50 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
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| D | insn-eval.c | 38 static bool is_string_insn(struct insn *insn) in is_string_insn() argument
40 insn_get_opcode(insn); in is_string_insn()
43 if (insn->opcode.nbytes != 1) in is_string_insn()
46 switch (insn->opcode.bytes[0]) { in is_string_insn()
64 bool insn_has_rep_prefix(struct insn *insn) in insn_has_rep_prefix() argument
69 insn_get_prefixes(insn); in insn_has_rep_prefix()
71 for_each_insn_prefix(insn, i, p) { in insn_has_rep_prefix()
93 static int get_seg_reg_override_idx(struct insn *insn) in get_seg_reg_override_idx() argument
99 insn_get_prefixes(insn); in get_seg_reg_override_idx()
102 for_each_insn_prefix(insn, i, p) { in get_seg_reg_override_idx()
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| /arch/x86/include/asm/ |
| D | insn.h | 68 struct insn { struct
134 extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
135 extern int insn_get_prefixes(struct insn *insn);
136 extern int insn_get_opcode(struct insn *insn);
137 extern int insn_get_modrm(struct insn *insn);
138 extern int insn_get_sib(struct insn *insn);
139 extern int insn_get_displacement(struct insn *insn);
140 extern int insn_get_immediate(struct insn *insn);
141 extern int insn_get_length(struct insn *insn);
151 extern int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m);
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| /arch/arm64/lib/ |
| D | insn.c | 42 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn) in aarch64_get_insn_class() argument
44 return aarch64_insn_encoding_class[(insn >> 25) & 0xf]; in aarch64_get_insn_class()
47 bool __kprobes aarch64_insn_is_steppable_hint(u32 insn) in aarch64_insn_is_steppable_hint() argument
49 if (!aarch64_insn_is_hint(insn)) in aarch64_insn_is_steppable_hint()
52 switch (insn & 0xFE0) { in aarch64_insn_is_steppable_hint()
71 bool aarch64_insn_is_branch_imm(u32 insn) in aarch64_insn_is_branch_imm() argument
73 return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) || in aarch64_insn_is_branch_imm()
74 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) || in aarch64_insn_is_branch_imm()
75 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) || in aarch64_insn_is_branch_imm()
76 aarch64_insn_is_bcond(insn)); in aarch64_insn_is_branch_imm()
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| /arch/powerpc/xmon/ |
| D | spu.h | 80 #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) argument
81 #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) argument
83 #define DECODE_INSN_RT(insn) (insn & 0x7f) argument
84 #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) argument
85 #define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) argument
86 #define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) argument
88 #define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) argument
89 #define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) argument
92 #define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) argument
93 #define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) argument
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| D | spu-dis.c | 44 get_index_for_opcode (unsigned int insn) in get_index_for_opcode() argument
47 unsigned int opcode = insn >> (32-11); in get_index_for_opcode()
83 print_insn_spu (unsigned long insn, unsigned long memaddr) in print_insn_spu() argument
90 index = get_index_for_opcode (insn); in print_insn_spu()
94 printf(".long 0x%lx", insn); in print_insn_spu()
106 int fb = (insn >> (32-18)) & 0x7f; in print_insn_spu()
127 DECODE_INSN_RT (insn)); in print_insn_spu()
131 DECODE_INSN_RA (insn)); in print_insn_spu()
135 DECODE_INSN_RB (insn)); in print_insn_spu()
139 DECODE_INSN_RC (insn)); in print_insn_spu()
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| /arch/s390/tools/ |
| D | gen_opcode_table.c | 22 struct insn { struct
44 struct insn *insn; argument
154 struct insn insn; in read_instructions() local
158 rc = scanf("%s %s %s", insn.opcode, insn.name, insn.format); in read_instructions()
163 insn.type = insn_format_to_type(insn.format); in read_instructions()
164 insn.name_len = strlen(insn.name); in read_instructions()
165 for (i = 0; i <= insn.name_len; i++) in read_instructions()
166 insn.upper[i] = toupper((unsigned char)insn.name[i]); in read_instructions()
168 desc->insn = realloc(desc->insn, desc->nr * sizeof(*desc->insn)); in read_instructions()
169 if (!desc->insn) in read_instructions()
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| /arch/csky/kernel/probes/ |
| D | decode-insn.c | 19 probe_opcode_t insn = le32_to_cpu(*addr); in csky_probe_decode_insn() local
21 CSKY_INSN_SET_SIMULATE(br16, insn); in csky_probe_decode_insn()
22 CSKY_INSN_SET_SIMULATE(bt16, insn); in csky_probe_decode_insn()
23 CSKY_INSN_SET_SIMULATE(bf16, insn); in csky_probe_decode_insn()
24 CSKY_INSN_SET_SIMULATE(jmp16, insn); in csky_probe_decode_insn()
25 CSKY_INSN_SET_SIMULATE(jsr16, insn); in csky_probe_decode_insn()
26 CSKY_INSN_SET_SIMULATE(lrw16, insn); in csky_probe_decode_insn()
27 CSKY_INSN_SET_SIMULATE(pop16, insn); in csky_probe_decode_insn()
29 CSKY_INSN_SET_SIMULATE(br32, insn); in csky_probe_decode_insn()
30 CSKY_INSN_SET_SIMULATE(bt32, insn); in csky_probe_decode_insn()
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| /arch/riscv/kernel/ |
| D | traps_misaligned.c | 85 #define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4) argument
118 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) argument
119 #define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) argument
120 #define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) argument
128 #define REG_OFFSET(insn, pos) \ argument
129 (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
131 #define REG_PTR(insn, pos, regs) \ argument
132 (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
134 #define GET_RM(insn) (((insn) >> 12) & 7) argument
136 #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) argument
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| /arch/arm64/kernel/probes/ |
| D | decode-insn.c | 18 static bool __kprobes aarch64_insn_is_steppable(u32 insn) in aarch64_insn_is_steppable() argument
27 if (aarch64_get_insn_class(insn) == AARCH64_INSN_CLS_BR_SYS) { in aarch64_insn_is_steppable()
28 if (aarch64_insn_is_branch(insn) || in aarch64_insn_is_steppable()
29 aarch64_insn_is_msr_imm(insn) || in aarch64_insn_is_steppable()
30 aarch64_insn_is_msr_reg(insn) || in aarch64_insn_is_steppable()
31 aarch64_insn_is_exception(insn) || in aarch64_insn_is_steppable()
32 aarch64_insn_is_eret(insn) || in aarch64_insn_is_steppable()
33 aarch64_insn_is_eret_auth(insn)) in aarch64_insn_is_steppable()
41 if (aarch64_insn_is_mrs(insn)) in aarch64_insn_is_steppable()
42 return aarch64_insn_extract_system_reg(insn) in aarch64_insn_is_steppable()
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| /arch/arm/probes/kprobes/ |
| D | actions-thumb.c | 24 t32_simulate_table_branch(probes_opcode_t insn, in t32_simulate_table_branch() argument
28 int rn = (insn >> 16) & 0xf; in t32_simulate_table_branch()
29 int rm = insn & 0xf; in t32_simulate_table_branch()
35 if (insn & 0x10) /* TBH */ in t32_simulate_table_branch()
44 t32_simulate_mrs(probes_opcode_t insn, in t32_simulate_mrs() argument
47 int rd = (insn >> 8) & 0xf; in t32_simulate_mrs()
53 t32_simulate_cond_branch(probes_opcode_t insn, in t32_simulate_cond_branch() argument
58 long offset = insn & 0x7ff; /* imm11 */ in t32_simulate_cond_branch()
59 offset += (insn & 0x003f0000) >> 5; /* imm6 */ in t32_simulate_cond_branch()
60 offset += (insn & 0x00002000) << 4; /* J1 */ in t32_simulate_cond_branch()
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| D | actions-common.c | 18 static void __kprobes simulate_ldm1stm1(probes_opcode_t insn, in simulate_ldm1stm1() argument
22 int rn = (insn >> 16) & 0xf; in simulate_ldm1stm1()
23 int lbit = insn & (1 << 20); in simulate_ldm1stm1()
24 int wbit = insn & (1 << 21); in simulate_ldm1stm1()
25 int ubit = insn & (1 << 23); in simulate_ldm1stm1()
26 int pbit = insn & (1 << 24); in simulate_ldm1stm1()
32 reg_bit_vector = insn & 0xffff; in simulate_ldm1stm1()
42 reg_bit_vector = insn & 0xffff; in simulate_ldm1stm1()
60 static void __kprobes simulate_stm1_pc(probes_opcode_t insn, in simulate_stm1_pc() argument
67 simulate_ldm1stm1(insn, asi, regs); in simulate_stm1_pc()
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| D | checkers-common.c | 13 enum probes_insn checker_stack_use_none(probes_opcode_t insn, in checker_stack_use_none() argument
21 enum probes_insn checker_stack_use_unknown(probes_opcode_t insn, in checker_stack_use_unknown() argument
30 enum probes_insn checker_stack_use_imm_0xx(probes_opcode_t insn, in checker_stack_use_imm_0xx() argument
34 int imm = insn & 0xff; in checker_stack_use_imm_0xx()
43 static enum probes_insn checker_stack_use_t32strd(probes_opcode_t insn, in checker_stack_use_t32strd() argument
47 int imm = insn & 0xff; in checker_stack_use_t32strd()
52 enum probes_insn checker_stack_use_imm_x0x(probes_opcode_t insn, in checker_stack_use_imm_x0x() argument
56 int imm = ((insn & 0xf00) >> 4) + (insn & 0xf); in checker_stack_use_imm_x0x()
62 enum probes_insn checker_stack_use_imm_xxx(probes_opcode_t insn, in checker_stack_use_imm_xxx() argument
66 int imm = insn & 0xfff; in checker_stack_use_imm_xxx()
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| /arch/s390/lib/ |
| D | probes.c | 12 int probe_is_prohibited_opcode(u16 *insn) in probe_is_prohibited_opcode() argument
14 if (!is_known_insn((unsigned char *)insn)) in probe_is_prohibited_opcode()
16 switch (insn[0] >> 8) { in probe_is_prohibited_opcode()
25 switch (insn[0] & 0x0f) { in probe_is_prohibited_opcode()
30 switch (insn[0]) { in probe_is_prohibited_opcode()
46 int probe_get_fixup_type(u16 *insn) in probe_get_fixup_type() argument
51 switch (insn[0] >> 8) { in probe_get_fixup_type()
56 if ((insn[0] & 0x0f) == 0) in probe_get_fixup_type()
77 if ((insn[0] & 0xff) == 0xb2) in probe_get_fixup_type()
81 if ((insn[0] & 0x0f) == 0x05) in probe_get_fixup_type()
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| /arch/mips/kernel/ |
| D | branch.c | 62 union mips_instruction insn = (union mips_instruction)dec_insn.insn; in __mm_isBranchInstr() local
68 switch (insn.mm_i_format.opcode) { in __mm_isBranchInstr()
70 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == in __mm_isBranchInstr()
72 switch (insn.mm_i_format.simmediate >> in __mm_isBranchInstr()
78 if (insn.mm_i_format.rt != 0) /* Not mm_jr */ in __mm_isBranchInstr()
79 regs->regs[insn.mm_i_format.rt] = in __mm_isBranchInstr()
83 *contpc = regs->regs[insn.mm_i_format.rs]; in __mm_isBranchInstr()
89 switch (insn.mm_i_format.rt) { in __mm_isBranchInstr()
97 if ((long)regs->regs[insn.mm_i_format.rs] < 0) in __mm_isBranchInstr()
100 (insn.mm_i_format.simmediate << 1); in __mm_isBranchInstr()
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| /arch/sparc/kernel/ |
| D | unaligned_32.c | 34 static inline enum direction decode_direction(unsigned int insn) in decode_direction() argument
36 unsigned long tmp = (insn >> 21) & 1; in decode_direction()
41 if(((insn>>19)&0x3f) == 15) in decode_direction()
49 static inline int decode_access_size(unsigned int insn) in decode_access_size() argument
51 insn = (insn >> 19) & 3; in decode_access_size()
53 if(!insn) in decode_access_size()
55 else if(insn == 3) in decode_access_size()
57 else if(insn == 2) in decode_access_size()
60 printk("Impossible unaligned trap. insn=%08x\n", insn); in decode_access_size()
67 static inline int decode_signedness(unsigned int insn) in decode_signedness() argument
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| /arch/arm64/kernel/ |
| D | armv8_deprecated.c | 48 u32 insn);
239 static bool try_emulate_swp(struct pt_regs *regs, u32 insn) in try_emulate_swp() argument
245 if ((insn & 0x0fb00ff0) != 0x01000090) in try_emulate_swp()
248 return swp_handler(regs, insn) == 0; in try_emulate_swp()
322 static bool try_emulate_cp15_barrier(struct pt_regs *regs, u32 insn) in try_emulate_cp15_barrier() argument
327 if ((insn & 0x0fff0fdf) == 0x0e070f9a) in try_emulate_cp15_barrier()
328 return cp15barrier_handler(regs, insn) == 0; in try_emulate_cp15_barrier()
330 if ((insn & 0x0fff0fff) == 0x0e070f95) in try_emulate_cp15_barrier()
331 return cp15barrier_handler(regs, insn) == 0; in try_emulate_cp15_barrier()
359 char *insn; in compat_setend_handler() local
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| /arch/riscv/kernel/probes/ |
| D | decode-insn.c | 19 probe_opcode_t insn = *addr; in riscv_probe_decode_insn() local
24 RISCV_INSN_REJECTED(system, insn); in riscv_probe_decode_insn()
25 RISCV_INSN_REJECTED(fence, insn); in riscv_probe_decode_insn()
32 RISCV_INSN_REJECTED(c_j, insn); in riscv_probe_decode_insn()
33 RISCV_INSN_REJECTED(c_jr, insn); in riscv_probe_decode_insn()
34 RISCV_INSN_REJECTED(c_jal, insn); in riscv_probe_decode_insn()
35 RISCV_INSN_REJECTED(c_jalr, insn); in riscv_probe_decode_insn()
36 RISCV_INSN_REJECTED(c_beqz, insn); in riscv_probe_decode_insn()
37 RISCV_INSN_REJECTED(c_bnez, insn); in riscv_probe_decode_insn()
38 RISCV_INSN_REJECTED(c_ebreak, insn); in riscv_probe_decode_insn()
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| /arch/nds32/include/asm/ |
| D | ftrace.h | 24 #define INSN_SIZE(insn) (((insn & 0x00000080) == 0) ? 4 : 2) argument
25 #define IS_SETHI(insn) ((insn & 0x000000fe) == 0x00000046) argument
26 #define ENDIAN_CONVERT(insn) be32_to_cpu(insn) argument
29 #define INSN_SIZE(insn) (((insn & 0x80000000) == 0) ? 4 : 2) argument
30 #define IS_SETHI(insn) ((insn & 0xfe000000) == 0x46000000) argument
31 #define ENDIAN_CONVERT(insn) (insn) argument
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| /arch/x86/tools/ |
| D | insn_decoder_test.c | 70 static void dump_insn(FILE *fp, struct insn *insn) in dump_insn() argument
73 dump_field(fp, "prefixes", "\t", &insn->prefixes); in dump_insn()
74 dump_field(fp, "rex_prefix", "\t", &insn->rex_prefix); in dump_insn()
75 dump_field(fp, "vex_prefix", "\t", &insn->vex_prefix); in dump_insn()
76 dump_field(fp, "opcode", "\t", &insn->opcode); in dump_insn()
77 dump_field(fp, "modrm", "\t", &insn->modrm); in dump_insn()
78 dump_field(fp, "sib", "\t", &insn->sib); in dump_insn()
79 dump_field(fp, "displacement", "\t", &insn->displacement); in dump_insn()
80 dump_field(fp, "immediate1", "\t", &insn->immediate1); in dump_insn()
81 dump_field(fp, "immediate2", "\t", &insn->immediate2); in dump_insn()
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| D | insn_sanity.c | 63 static void dump_insn(FILE *fp, struct insn *insn) in dump_insn() argument
66 dump_field(fp, "prefixes", "\t", &insn->prefixes); in dump_insn()
67 dump_field(fp, "rex_prefix", "\t", &insn->rex_prefix); in dump_insn()
68 dump_field(fp, "vex_prefix", "\t", &insn->vex_prefix); in dump_insn()
69 dump_field(fp, "opcode", "\t", &insn->opcode); in dump_insn()
70 dump_field(fp, "modrm", "\t", &insn->modrm); in dump_insn()
71 dump_field(fp, "sib", "\t", &insn->sib); in dump_insn()
72 dump_field(fp, "displacement", "\t", &insn->displacement); in dump_insn()
73 dump_field(fp, "immediate1", "\t", &insn->immediate1); in dump_insn()
74 dump_field(fp, "immediate2", "\t", &insn->immediate2); in dump_insn()
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| /arch/arm64/kvm/ |
| D | va_layout.c | 114 u32 insn = AARCH64_BREAK_FAULT; in compute_instruction() local
118 insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND, in compute_instruction()
125 insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT, in compute_instruction()
131 insn = aarch64_insn_gen_add_sub_imm(rd, rn, in compute_instruction()
138 insn = aarch64_insn_gen_add_sub_imm(rd, rn, in compute_instruction()
146 insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT, in compute_instruction()
151 return insn; in compute_instruction()
162 u32 rd, rn, insn, oinsn; in kvm_update_va_mask() local
181 insn = compute_instruction(i, rd, rn); in kvm_update_va_mask()
182 BUG_ON(insn == AARCH64_BREAK_FAULT); in kvm_update_va_mask()
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| /arch/arm/probes/ |
| D | decode.c | 196 prepare_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi, in prepare_emulated_insn() argument
201 u16 *thumb_insn = (u16 *)asi->insn; in prepare_emulated_insn()
205 return insn; in prepare_emulated_insn()
207 asi->insn[1] = __opcode_to_mem_arm(0xe12fff1e); /* ARM bx lr */ in prepare_emulated_insn()
209 asi->insn[1] = __opcode_to_mem_arm(0xe1a0f00e); /* mov pc, lr */ in prepare_emulated_insn()
212 if (insn < 0xe0000000) in prepare_emulated_insn()
213 insn = (insn | 0xe0000000) & ~0x10000000; in prepare_emulated_insn()
214 return insn; in prepare_emulated_insn()
222 set_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi, in set_emulated_insn() argument
227 u16 *ip = (u16 *)asi->insn; in set_emulated_insn()
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| /arch/x86/kernel/ |
| D | uprobes.c | 41 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) argument
42 #define OPCODE2(insn) ((insn)->opcode.bytes[1]) argument
43 #define OPCODE3(insn) ((insn)->opcode.bytes[2]) argument
44 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) argument
256 static bool is_prefix_bad(struct insn *insn) in is_prefix_bad() argument
261 for_each_insn_prefix(insn, i, p) { in is_prefix_bad()
277 static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64) in uprobe_init_insn() argument
283 ret = insn_decode(insn, auprobe->insn, sizeof(auprobe->insn), m); in uprobe_init_insn()
287 if (is_prefix_bad(insn)) in uprobe_init_insn()
291 if (insn_masking_exception(insn)) in uprobe_init_insn()
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| D | umip.c | 151 static int identify_insn(struct insn *insn) in identify_insn() argument
154 insn_get_modrm(insn); in identify_insn()
156 if (!insn->modrm.nbytes) in identify_insn()
160 if (insn->opcode.bytes[0] != 0xf) in identify_insn()
163 if (insn->opcode.bytes[1] == 0x1) { in identify_insn()
164 switch (X86_MODRM_REG(insn->modrm.value)) { in identify_insn()
174 } else if (insn->opcode.bytes[1] == 0x0) { in identify_insn()
175 if (X86_MODRM_REG(insn->modrm.value) == 0) in identify_insn()
177 else if (X86_MODRM_REG(insn->modrm.value) == 1) in identify_insn()
205 static int emulate_umip_insn(struct insn *insn, int umip_inst, in emulate_umip_insn() argument
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