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Searched refs:irq_mask (Results 1 – 25 of 174) sorted by relevance

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/arch/arm/mach-pxa/
Dpxa_cplds_irqs.c29 unsigned int irq_mask; member
41 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; in cplds_irq_handler()
55 fpga->irq_mask &= ~bit; in cplds_irq_mask()
56 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_irq_mask()
68 fpga->irq_mask |= bit; in cplds_irq_unmask()
69 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_irq_unmask()
75 .irq_mask = cplds_irq_mask,
100 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_resume()
137 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); in cplds_probe()
/arch/alpha/kernel/
Dsys_rx164.c40 volatile unsigned int *irq_mask; in rx164_update_irq_hw() local
42 irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74); in rx164_update_irq_hw()
43 *irq_mask = mask; in rx164_update_irq_hw()
45 *irq_mask; in rx164_update_irq_hw()
63 .irq_mask = rx164_disable_irq,
/arch/mips/sgi-ip27/
Dip27-irq.c27 u64 *irq_mask[2]; member
56 __raw_writeq(mask[0], hd->irq_mask[0]); in enable_hub_irq()
57 __raw_writeq(mask[1], hd->irq_mask[1]); in enable_hub_irq()
66 __raw_writeq(mask[0], hd->irq_mask[0]); in disable_hub_irq()
67 __raw_writeq(mask[1], hd->irq_mask[1]); in disable_hub_irq()
82 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A); in setup_hub_mask()
83 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A); in setup_hub_mask()
85 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B); in setup_hub_mask()
86 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B); in setup_hub_mask()
113 .irq_mask = disable_hub_irq,
/arch/arm/mach-omap2/
Ddisplay.c282 u32 v, irq_mask = 0; in dispc_disable_outputs() local
326 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; in dispc_disable_outputs()
330 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; in dispc_disable_outputs()
332 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | in dispc_disable_outputs()
338 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; in dispc_disable_outputs()
340 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; in dispc_disable_outputs()
346 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); in dispc_disable_outputs()
368 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != in dispc_disable_outputs()
369 irq_mask) { in dispc_disable_outputs()
/arch/mips/loongson2ef/lemote-2f/
Dpm.c54 int irq_mask; in setup_wakeup_events() local
61 irq_mask = inb(PIC_MASTER_IMR); in setup_wakeup_events()
67 outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR); in setup_wakeup_events()
/arch/arm/mach-cns3xxx/
Dcore.c198 u32 irq_mask; in __cns3xxx_timer_init() local
217 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
218 irq_mask &= ~(1 << 2); in __cns3xxx_timer_init()
219 irq_mask |= 0x03; in __cns3xxx_timer_init()
220 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
232 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
233 irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); in __cns3xxx_timer_init()
234 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
/arch/mips/sgi-ip32/
Dip32-irq.c140 .irq_mask = crime_disable_irq,
160 .irq_mask = crime_disable_irq,
193 .irq_mask = disable_macepci_irq,
292 .irq_mask = disable_maceisa_irq,
299 .irq_mask = disable_maceisa_irq,
327 .irq_mask = disable_mace_irq,
/arch/mips/dec/
Dioasic-irq.c45 .irq_mask = mask_ioasic_irq,
62 .irq_mask = mask_ioasic_irq,
/arch/mips/sgi-ip22/
Dip22-int.c50 .irq_mask = disable_local0_irq,
69 .irq_mask = disable_local1_irq,
88 .irq_mask = disable_local2_irq,
107 .irq_mask = disable_local3_irq,
/arch/arm/mach-omap1/
Dfpga.c109 .irq_mask = fpga_mask_irq,
117 .irq_mask = fpga_mask_irq,
/arch/mips/kernel/
Dirq-msc01.c101 .irq_mask = mask_msc_irq,
110 .irq_mask = mask_msc_irq,
/arch/powerpc/platforms/52xx/
Dmpc52xx_pic.c206 .irq_mask = mpc52xx_extirq_mask,
234 .irq_mask = mpc52xx_main_mask,
257 .irq_mask = mpc52xx_periph_mask,
286 .irq_mask = mpc52xx_sdma_mask,
/arch/arm/plat-orion/
Dirq.c35 ct->chip.irq_mask = irq_gc_mask_clr_bit; in orion_irq_init()
/arch/arm/mach-rpc/
Dirq.c62 .irq_mask = iomd_irq_mask,
67 .irq_mask = iomd_irq_mask,
/arch/arm/mach-footbridge/
Disa-irq.c54 .irq_mask = isa_mask_pic_lo_irq,
83 .irq_mask = isa_mask_pic_hi_irq,
/arch/m68k/coldfire/
Dintc-simr.c164 .irq_mask = intc_irq_mask,
171 .irq_mask = intc_irq_mask,
Dintc-2.c180 .irq_mask = intc_irq_mask,
187 .irq_mask = intc_irq_mask,
/arch/powerpc/include/asm/
Dfsl_pm.h25 void (*irq_mask)(int cpu); member
/arch/x86/kernel/apic/
Dmsi.c151 .irq_mask = pci_msi_mask_irq,
222 .irq_mask = pci_msi_mask_irq,
274 .irq_mask = dmar_msi_mask,
/arch/mips/loongson2ef/common/
Dbonito-irq.c29 .irq_mask = bonito_irq_disable,
/arch/arm/kernel/
Dmachine_kexec.c143 if (chip->irq_mask) in machine_kexec_mask_interrupts()
144 chip->irq_mask(&desc->irq_data); in machine_kexec_mask_interrupts()
/arch/hexagon/kernel/
Dirq_cpu.c47 .irq_mask = mask_irq,
/arch/mips/ar7/
Dirq.c75 .irq_mask = ar7_mask_irq,
82 .irq_mask = ar7_mask_sec_irq,
/arch/riscv/kernel/
Dmachine_kexec.c182 if (chip->irq_mask) in machine_kexec_mask_interrupts()
183 chip->irq_mask(&desc->irq_data); in machine_kexec_mask_interrupts()
/arch/sh/kernel/cpu/irq/
Dimask.c76 .irq_mask = mask_imask_irq,

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