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Searched refs:mtdcr (Results 1 – 9 of 9) sorted by relevance

/arch/powerpc/platforms/4xx/
Dsoc.c34 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr); in l2c_diag()
35 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG); in l2c_diag()
61 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0); in l2c_error_handler()
62 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); in l2c_error_handler()
125 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC, in ppc4xx_l2c_probe()
127 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR, in ppc4xx_l2c_probe()
129 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR, in ppc4xx_l2c_probe()
131 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR, in ppc4xx_l2c_probe()
133 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR, in ppc4xx_l2c_probe()
140 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r); in ppc4xx_l2c_probe()
[all …]
Duic.c61 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
64 mtdcr(uic->dcrbase + UIC_ER, er); in uic_unmask_irq()
78 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_irq()
89 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); in uic_ack_irq()
104 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_ack_irq()
114 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
155 mtdcr(uic->dcrbase + UIC_PR, pr); in uic_set_irq_type()
156 mtdcr(uic->dcrbase + UIC_TR, tr); in uic_set_irq_type()
157 mtdcr(uic->dcrbase + UIC_SR, ~mask); in uic_set_irq_type()
261 mtdcr(uic->dcrbase + UIC_ER, 0); in uic_init_one()
[all …]
/arch/powerpc/boot/
Ddcr.h11 #define mtdcr(rn, val) \ macro
29 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
32 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
33 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
182 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
185 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
186 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
200 mtdcr(DCRN_CPR0_CFGADDR, offset); \
203 mtdcr(DCRN_CPR0_CFGADDR, offset); \
204 mtdcr(DCRN_CPR0_CFGDATA, data); })
D4xx.c296 mtdcr(DCRN_MAL0_CFG, MAL_RESET); in ibm4xx_quiesce_eth()
312 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); in ibm4xx_fixup_ebc_ranges()
609 mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); in ibm405gp_fixup_clocks()
/arch/powerpc/platforms/44x/
Dfsp2.h249 mtdcr(DCRN_CMU_ADDR, reg); \
250 mtdcr(DCRN_CMU_DATA, data); \
255 mtdcr(DCRN_CMU_ADDR, reg); \
261 mtdcr(DCRN_L2CDCRAI, reg); \
262 mtdcr(DCRN_L2CDCRDI, data); \
267 mtdcr(DCRN_L2CDCRAI, reg); \
Dfsp2.c253 mtdcr(DCRN_PLB6_BASE, val); in fsp2_probe()
254 mtdcr(DCRN_PLB6_HD, 0xffff0000); in fsp2_probe()
255 mtdcr(DCRN_PLB6_SHD, 0xffff0000); in fsp2_probe()
299 mtdcr(DCRN_CONF_EIR_RS, 0x80000000); in fsp2_probe()
/arch/powerpc/sysdev/
Ddcr-low.S37 mtdcr 0,r4; blr
42 mtdcr dcr,r4; blr
/arch/powerpc/include/asm/
Ddcr-native.h30 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
64 #define mtdcr(rn, v) \ macro
/arch/powerpc/kernel/
Dcpu_setup_44x.S66 mtdcr DCRN_PLB4A0_ACR,r3