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Searched refs:mtdcri (Results 1 – 3 of 3) sorted by relevance

/arch/powerpc/platforms/4xx/
Dpci.c743 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
744 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
745 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
857 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
860 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
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Dmsi.c172 mtdcri(SDR0, *sdr_addr, upper_32_bits(res.start)); /*HIGH addr */ in ppc4xx_setup_pcieh_hw()
173 mtdcri(SDR0, *sdr_addr + 1, lower_32_bits(res.start)); /* Low addr */ in ppc4xx_setup_pcieh_hw()
/arch/powerpc/include/asm/
Ddcr-native.h134 #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \ macro