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Searched refs:n0 (Results 1 – 16 of 16) sorted by relevance

/arch/alpha/lib/
Dudiv-qrnnd.S45 #define n0 $18 macro
53 $loop1: cmplt n0,0,tmp
56 addq n0,n0,n0
60 bis n0,qb,n0
61 cmplt n0,0,tmp
64 addq n0,n0,n0
68 bis n0,qb,n0
69 cmplt n0,0,tmp
72 addq n0,n0,n0
76 bis n0,qb,n0
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/arch/powerpc/math-emu/
Dudivmodti4.c11 _FP_W_TYPE n1, _FP_W_TYPE n0, in _fp_udivmodti4() argument
24 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
37 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
42 r0 = n0; in _fp_udivmodti4()
59 n1 = (n1 << bm) | (n0 >> (_FP_W_TYPE_SIZE - bm)); in _fp_udivmodti4()
60 n0 = n0 << bm; in _fp_udivmodti4()
63 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
99 n1 = (n1 << bm) | (n0 >> b); in _fp_udivmodti4()
100 n0 = n0 << bm; in _fp_udivmodti4()
107 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
[all …]
/arch/mips/ralink/
Drt305x.c147 u32 n0; in prom_soc_init() local
151 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); in prom_soc_init()
154 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { in prom_soc_init()
167 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { in prom_soc_init()
171 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { in prom_soc_init()
175 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { in prom_soc_init()
180 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); in prom_soc_init()
Drt288x.c64 u32 n0; in prom_soc_init() local
68 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); in prom_soc_init()
72 if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { in prom_soc_init()
76 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1); in prom_soc_init()
Drt3883.c77 u32 n0; in prom_soc_init() local
81 n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); in prom_soc_init()
85 if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) { in prom_soc_init()
89 panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1); in prom_soc_init()
Dmt7620.c331 u32 n0; in prom_soc_init() local
339 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); in prom_soc_init()
344 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { in prom_soc_init()
354 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { in prom_soc_init()
366 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); in prom_soc_init()
/arch/sparc/math-emu/
Dsfp-util_64.h76 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
85 __r1 = (__r1 << 32) | (n0 >> 32); \
98 __r0 = (__r0 << 32) | ((USItype)n0); \
Dsfp-util_32.h77 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
106 "0" ((USItype)(n0)) : "%g1", "cc")
/arch/sh/math-emu/
Dsfp-util.h32 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
42 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
55 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
/arch/alpha/math-emu/
Dsfp-util.h21 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
23 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
/arch/nds32/include/asm/
Dsfp-machine.h128 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
137 __r1 = __r1 * __ll_B | __ll_highpart(n0); \
148 __r0 = __r0 * __ll_B | __ll_lowpart(n0); \
/arch/alpha/kernel/
Dperf_event.c437 int n0; in alpha_pmu_add() local
456 n0 = cpuc->n_events; in alpha_pmu_add()
457 if (n0 < alpha_pmu->num_pmcs) { in alpha_pmu_add()
458 cpuc->event[n0] = event; in alpha_pmu_add()
459 cpuc->evtype[n0] = event->hw.event_base; in alpha_pmu_add()
460 cpuc->current_idx[n0] = PMC_NO_INDEX; in alpha_pmu_add()
462 if (!alpha_check_constraints(cpuc->event, cpuc->evtype, n0+1)) { in alpha_pmu_add()
/arch/powerpc/include/asm/
Dsfp-machine.h280 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
290 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
303 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
/arch/sparc/kernel/
Dperf_event.c1375 int n0, ret = -EAGAIN; in sparc_pmu_add() local
1380 n0 = cpuc->n_events; in sparc_pmu_add()
1381 if (n0 >= sparc_pmu->max_hw_events) in sparc_pmu_add()
1384 cpuc->event[n0] = event; in sparc_pmu_add()
1385 cpuc->events[n0] = event->hw.event_base; in sparc_pmu_add()
1386 cpuc->current_idx[n0] = PIC_NO_INDEX; in sparc_pmu_add()
1400 if (check_excludes(cpuc->event, n0, 1)) in sparc_pmu_add()
1402 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) in sparc_pmu_add()
/arch/powerpc/perf/
Dcore-book3s.c1601 int n0; in power_pmu_add() local
1612 n0 = cpuhw->n_events; in power_pmu_add()
1613 if (n0 >= ppmu->n_counter) in power_pmu_add()
1615 cpuhw->event[n0] = event; in power_pmu_add()
1616 cpuhw->events[n0] = event->hw.config; in power_pmu_add()
1617 cpuhw->flags[n0] = event->hw.event_base; in power_pmu_add()
1638 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) in power_pmu_add()
1640 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1, cpuhw->event)) in power_pmu_add()
1642 event->hw.config = cpuhw->events[n0]; in power_pmu_add()
/arch/x86/events/
Dcore.c977 int n0, i, wmin, wmax, unsched = 0; in x86_schedule_events() local
988 n0 = cpuc->n_events; in x86_schedule_events()
990 n0 -= cpuc->n_txn; in x86_schedule_events()
1001 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0)); in x86_schedule_events()
1093 for (i = n0; i < n; i++) { in x86_schedule_events()
1447 int n, n0, ret; in x86_pmu_add() local
1451 n0 = cpuc->n_events; in x86_pmu_add()
1486 cpuc->n_added += n - n0; in x86_pmu_add()
1487 cpuc->n_txn += n - n0; in x86_pmu_add()