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/arch/mips/include/asm/octeon/
Dcvmx-pexp-defs.h31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31… argument
43 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7)… argument
44 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) … argument
45 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset)… argument
46 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) … argument
68 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset argument
92 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) … argument
93 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset)… argument
94 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((o… argument
95 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((of… argument
[all …]
Dcvmx-pcsx-defs.h31 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) in CVMX_PCSX_ANX_ADV_REG() argument
35 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
38 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
42 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
44 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
46 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
49 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) in CVMX_PCSX_ANX_EXT_ST_REG() argument
53 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
56 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
60 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
[all …]
Dcvmx-asm.h93 #define CVMX_PREPARE_FOR_STORE(address, offset) \ argument
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
101 #define CVMX_DONT_WRITE_BACK(address, offset) \ argument
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
117 #define CVMX_CACHE(op, address, offset) \ argument
118 asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
121 #define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) argument
123 #define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) argument
125 #define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) argument
127 #define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) argument
/arch/sh/boards/mach-microdev/
Dio.c55 void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len) in microdev_ioport_map() argument
59 if ((offset >= IO_LAN91C111_BASE) && in microdev_ioport_map()
60 (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { in microdev_ioport_map()
64 result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; in microdev_ioport_map()
65 } else if ((offset >= IO_SUPERIO_BASE) && in microdev_ioport_map()
66 (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { in microdev_ioport_map()
72 result = IO_SUPERIO_PHYS + (offset << 1); in microdev_ioport_map()
73 } else if (((offset >= IO_IDE1_BASE) && in microdev_ioport_map()
74 (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || in microdev_ioport_map()
75 (offset == IO_IDE1_MISC)) { in microdev_ioport_map()
[all …]
/arch/riscv/include/asm/
Dftrace.h69 #define to_jalr_t0(offset) \ argument
70 (((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_T0)
72 #define to_auipc_t0(offset) \ argument
73 ((offset & JALR_SIGN_MASK) ? \
74 (((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_T0) : \
75 ((offset & AUIPC_OFFSET_MASK) | AUIPC_T0))
79 unsigned int offset = \
81 call[0] = to_auipc_t0(offset); \
82 call[1] = to_jalr_t0(offset); \
85 #define to_jalr_ra(offset) \ argument
[all …]
/arch/x86/include/asm/numachip/
Dnumachip_csr.h39 static inline void *lcsr_address(unsigned long offset) in lcsr_address() argument
42 CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK)); in lcsr_address()
45 static inline unsigned int read_lcsr(unsigned long offset) in read_lcsr() argument
47 return swab32(readl(lcsr_address(offset))); in read_lcsr()
50 static inline void write_lcsr(unsigned long offset, unsigned int val) in write_lcsr() argument
52 writel(swab32(val), lcsr_address(offset)); in write_lcsr()
67 static inline void __iomem *numachip2_lcsr_address(unsigned long offset) in numachip2_lcsr_address() argument
70 (offset & (NUMACHIP2_LCSR_SIZE - 1))); in numachip2_lcsr_address()
73 static inline u32 numachip2_read32_lcsr(unsigned long offset) in numachip2_read32_lcsr() argument
75 return readl(numachip2_lcsr_address(offset)); in numachip2_read32_lcsr()
[all …]
/arch/arm/kernel/
Dmodule.c85 s32 offset; in apply_relocate() local
91 offset = ELF32_R_SYM(rel->r_info); in apply_relocate()
92 if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) { in apply_relocate()
98 sym = ((Elf32_Sym *)symsec->sh_addr) + offset; in apply_relocate()
129 offset = __mem_to_opcode_arm(*(u32 *)loc); in apply_relocate()
130 offset = (offset & 0x00ffffff) << 2; in apply_relocate()
131 if (offset & 0x02000000) in apply_relocate()
132 offset -= 0x04000000; in apply_relocate()
134 offset += sym->st_value - loc; in apply_relocate()
143 (offset <= (s32)0xfe000000 || in apply_relocate()
[all …]
Dinsn.c12 long offset; in __arm_gen_branch_thumb2() local
14 offset = (long)addr - (long)(pc + 4); in __arm_gen_branch_thumb2()
15 if (offset < -16777216 || offset > 16777214) { in __arm_gen_branch_thumb2()
20 s = (offset >> 24) & 0x1; in __arm_gen_branch_thumb2()
21 i1 = (offset >> 23) & 0x1; in __arm_gen_branch_thumb2()
22 i2 = (offset >> 22) & 0x1; in __arm_gen_branch_thumb2()
23 imm10 = (offset >> 12) & 0x3ff; in __arm_gen_branch_thumb2()
24 imm11 = (offset >> 1) & 0x7ff; in __arm_gen_branch_thumb2()
41 long offset; in __arm_gen_branch_arm() local
46 offset = (long)addr - (long)(pc + 8); in __arm_gen_branch_arm()
[all …]
/arch/sparc/lib/
Dbitext.c30 int offset, count; /* siamese twins */ in bit_map_string_get() local
55 offset = t->first_free; in bit_map_string_get()
57 offset = t->last_off & ~align1; in bit_map_string_get()
60 off_new = find_next_zero_bit(t->map, t->size, offset); in bit_map_string_get()
62 count += off_new - offset; in bit_map_string_get()
63 offset = off_new; in bit_map_string_get()
64 if (offset >= t->size) in bit_map_string_get()
65 offset = 0; in bit_map_string_get()
70 t->size, t->used, offset, len, align, count); in bit_map_string_get()
74 if (offset + len > t->size) { in bit_map_string_get()
[all …]
Dblockops.S15 #define BLAST_BLOCK(buf, offset) \ argument
16 std %g0, [buf + offset + 0x38]; \
17 std %g0, [buf + offset + 0x30]; \
18 std %g0, [buf + offset + 0x28]; \
19 std %g0, [buf + offset + 0x20]; \
20 std %g0, [buf + offset + 0x18]; \
21 std %g0, [buf + offset + 0x10]; \
22 std %g0, [buf + offset + 0x08]; \
23 std %g0, [buf + offset + 0x00];
28 #define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
[all …]
/arch/mips/boot/compressed/
Duart-16550.c13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) argument
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) argument
23 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset)) argument
28 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) argument
34 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) argument
46 static inline unsigned int serial_in(int offset) in serial_in() argument
48 return *((volatile IOTYPE *)PORT(offset)) & 0xFF; in serial_in()
51 static inline void serial_out(int offset, int value) in serial_out() argument
53 *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; in serial_out()
/arch/ia64/include/asm/uv/
Duv_hub.h172 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) in uv_pnode_offset_to_vaddr() argument
174 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); in uv_pnode_offset_to_vaddr()
183 unsigned long offset) in uv_global_mmr32_address() argument
186 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); in uv_global_mmr32_address()
189 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, in uv_write_global_mmr32() argument
192 *uv_global_mmr32_address(pnode, offset) = val; in uv_write_global_mmr32()
196 unsigned long offset) in uv_read_global_mmr32() argument
198 return *uv_global_mmr32_address(pnode, offset); in uv_read_global_mmr32()
206 unsigned long offset) in uv_global_mmr64_address() argument
209 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); in uv_global_mmr64_address()
[all …]
/arch/powerpc/platforms/cell/spufs/
Dspu_restore.c69 unsigned int offset; in restore_decr() local
78 offset = LSCSA_QW_OFFSET(decr_status); in restore_decr()
79 decr_running = regs_spill[offset].slot[0] & SPU_DECR_STATUS_RUNNING; in restore_decr()
81 offset = LSCSA_QW_OFFSET(decr); in restore_decr()
82 decr = regs_spill[offset].slot[0]; in restore_decr()
89 unsigned int offset; in write_ppu_mb() local
96 offset = LSCSA_QW_OFFSET(ppu_mb); in write_ppu_mb()
97 data = regs_spill[offset].slot[0]; in write_ppu_mb()
103 unsigned int offset; in write_ppuint_mb() local
110 offset = LSCSA_QW_OFFSET(ppuint_mb); in write_ppuint_mb()
[all …]
Dspu_save.c27 unsigned int offset; in save_event_mask() local
32 offset = LSCSA_QW_OFFSET(event_mask); in save_event_mask()
33 regs_spill[offset].slot[0] = spu_readch(SPU_RdEventMask); in save_event_mask()
38 unsigned int offset; in save_tag_mask() local
43 offset = LSCSA_QW_OFFSET(tag_mask); in save_tag_mask()
44 regs_spill[offset].slot[0] = spu_readch(MFC_RdTagMask); in save_tag_mask()
70 unsigned int offset; in save_fpcr() local
76 offset = LSCSA_QW_OFFSET(fpcr); in save_fpcr()
77 regs_spill[offset].v = spu_mffpscr(); in save_fpcr()
82 unsigned int offset; in save_decr() local
[all …]
/arch/x86/pci/
Dearly.c11 u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config() argument
14 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
19 u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_byte() argument
22 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
23 v = inb(0xcfc + (offset&3)); in read_pci_config_byte()
27 u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_16() argument
30 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
31 v = inw(0xcfc + (offset&2)); in read_pci_config_16()
35 void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, in write_pci_config() argument
38 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
[all …]
/arch/mips/alchemy/common/
Dgpiolib.c40 static int gpio2_get(struct gpio_chip *chip, unsigned offset) in gpio2_get() argument
42 return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); in gpio2_get()
45 static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value) in gpio2_set() argument
47 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); in gpio2_set()
50 static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) in gpio2_direction_input() argument
52 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); in gpio2_direction_input()
55 static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, in gpio2_direction_output() argument
58 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, in gpio2_direction_output()
62 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) in gpio2_to_irq() argument
64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); in gpio2_to_irq()
[all …]
/arch/riscv/kernel/
Dmodule.c49 ptrdiff_t offset = (void *)v - (void *)location; in apply_r_riscv_branch_rela() local
50 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
51 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
52 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
53 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
62 ptrdiff_t offset = (void *)v - (void *)location; in apply_r_riscv_jal_rela() local
63 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
64 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
65 u32 imm11 = (offset & 0x800) << (20 - 11); in apply_r_riscv_jal_rela()
66 u32 imm10_1 = (offset & 0x7fe) << (30 - 10); in apply_r_riscv_jal_rela()
[all …]
/arch/mips/kernel/
Drelocate.c27 #define RELOCATED(x) ((void *)((long)x + offset))
42 int __weak plat_post_relocation(long offset) in plat_post_relocation() argument
74 static void __init apply_r_mips_64_rel(u32 *loc_new, long offset) in apply_r_mips_64_rel() argument
76 *(u64 *)loc_new += offset; in apply_r_mips_64_rel()
79 static void __init apply_r_mips_32_rel(u32 *loc_new, long offset) in apply_r_mips_32_rel() argument
81 *loc_new += offset; in apply_r_mips_32_rel()
84 static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset) in apply_r_mips_26_rel() argument
88 if (offset % 4) { in apply_r_mips_26_rel()
98 target_addr += offset; in apply_r_mips_26_rel()
115 long offset) in apply_r_mips_hi16_rel() argument
[all …]
/arch/x86/kvm/vmx/
Devmcs.h71 u16 offset; member
95 return evmcs_field->offset; in get_evmcs_offset()
101 int offset = get_evmcs_offset(field, &clean_field); in evmcs_write64() local
103 if (offset < 0) in evmcs_write64()
106 *(u64 *)((char *)current_evmcs + offset) = value; in evmcs_write64()
114 int offset = get_evmcs_offset(field, &clean_field); in evmcs_write32() local
116 if (offset < 0) in evmcs_write32()
119 *(u32 *)((char *)current_evmcs + offset) = value; in evmcs_write32()
126 int offset = get_evmcs_offset(field, &clean_field); in evmcs_write16() local
128 if (offset < 0) in evmcs_write16()
[all …]
/arch/m68k/include/asm/
Dmac_psc.h222 static inline void psc_write_byte(int offset, __u8 data) in psc_write_byte() argument
224 *((volatile __u8 *)(psc + offset)) = data; in psc_write_byte()
227 static inline void psc_write_word(int offset, __u16 data) in psc_write_word() argument
229 *((volatile __u16 *)(psc + offset)) = data; in psc_write_word()
232 static inline void psc_write_long(int offset, __u32 data) in psc_write_long() argument
234 *((volatile __u32 *)(psc + offset)) = data; in psc_write_long()
237 static inline u8 psc_read_byte(int offset) in psc_read_byte() argument
239 return *((volatile __u8 *)(psc + offset)); in psc_read_byte()
242 static inline u16 psc_read_word(int offset) in psc_read_word() argument
244 return *((volatile __u16 *)(psc + offset)); in psc_read_word()
[all …]
/arch/m68k/coldfire/
Dgpio.c110 static int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset) in mcfgpio_direction_input() argument
112 return __mcfgpio_direction_input(offset); in mcfgpio_direction_input()
115 static int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset) in mcfgpio_get_value() argument
117 return !!__mcfgpio_get_value(offset); in mcfgpio_get_value()
120 static int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, in mcfgpio_direction_output() argument
123 return __mcfgpio_direction_output(offset, value); in mcfgpio_direction_output()
126 static void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, in mcfgpio_set_value() argument
129 __mcfgpio_set_value(offset, value); in mcfgpio_set_value()
132 static int mcfgpio_request(struct gpio_chip *chip, unsigned offset) in mcfgpio_request() argument
134 return __mcfgpio_request(offset); in mcfgpio_request()
[all …]
/arch/mips/rb532/
Dgpio.c61 unsigned offset, void __iomem *ioaddr) in rb532_set_bit() argument
69 val &= ~(!bitval << offset); /* unset bit if bitval == 0 */ in rb532_set_bit()
70 val |= (!!bitval << offset); /* set bit if bitval == 1 */ in rb532_set_bit()
80 static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) in rb532_get_bit() argument
82 return readl(ioaddr) & (1 << offset); in rb532_get_bit()
87 static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) in rb532_gpio_get() argument
92 return !!rb532_get_bit(offset, gpch->regbase + GPIOD); in rb532_gpio_get()
99 unsigned offset, int value) in rb532_gpio_set() argument
104 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_set()
110 static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in rb532_gpio_direction_input() argument
[all …]
/arch/xtensa/include/asm/
Dio.h35 static inline void __iomem *ioremap(unsigned long offset, unsigned long size) in ioremap() argument
37 if (offset >= XCHAL_KIO_PADDR in ioremap()
38 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) in ioremap()
39 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR); in ioremap()
41 return xtensa_ioremap_nocache(offset, size); in ioremap()
44 static inline void __iomem *ioremap_cache(unsigned long offset, in ioremap_cache() argument
47 if (offset >= XCHAL_KIO_PADDR in ioremap_cache()
48 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) in ioremap_cache()
49 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR); in ioremap_cache()
51 return xtensa_ioremap_cache(offset, size); in ioremap_cache()
/arch/x86/platform/ce4100/
Dce4100.c36 static unsigned int mem_serial_in(struct uart_port *p, int offset) in mem_serial_in() argument
38 offset = offset << p->regshift; in mem_serial_in()
39 return readl(p->membase + offset); in mem_serial_in()
52 static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset) in ce4100_mem_serial_in() argument
56 if (offset == UART_IIR) { in ce4100_mem_serial_in()
57 offset = offset << p->regshift; in ce4100_mem_serial_in()
58 ret = readl(p->membase + offset); in ce4100_mem_serial_in()
72 ret = mem_serial_in(p, offset); in ce4100_mem_serial_in()
76 static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value) in ce4100_mem_serial_out() argument
78 offset = offset << p->regshift; in ce4100_mem_serial_out()
[all …]
/arch/mips/include/asm/mach-bcm63xx/
Dioremap.h7 static inline int is_bcm63xx_internal_registers(phys_addr_t offset) in is_bcm63xx_internal_registers() argument
11 if (offset >= 0xfff80000) in is_bcm63xx_internal_registers()
18 if (offset >= 0xfff00000) in is_bcm63xx_internal_registers()
24 if (offset >= 0xb0000000 && offset < 0xb1000000) in is_bcm63xx_internal_registers()
31 static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, in plat_ioremap() argument
34 if (is_bcm63xx_internal_registers(offset)) in plat_ioremap()
35 return (void __iomem *)offset; in plat_ioremap()

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