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Searched refs:omap_ctrl_readl (Results 1 – 9 of 9) sorted by relevance

/arch/arm/mach-omap2/
Dcontrol.c144 val = omap_ctrl_readl(offset); in omap_ctrl_readb()
154 val = omap_ctrl_readl(offset); in omap_ctrl_readw()
159 u32 omap_ctrl_readl(u16 offset) in omap_ctrl_readl() function
171 tmp = omap_ctrl_readl(offset); in omap_ctrl_writeb()
184 tmp = omap_ctrl_readl(offset); in omap_ctrl_writew()
415 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); in omap3_control_save_context()
416 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); in omap3_control_save_context()
418 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); in omap3_control_save_context()
420 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); in omap3_control_save_context()
422 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); in omap3_control_save_context()
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Domap_phy_internal.c61 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
69 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
81 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); in am35x_musb_phy_power()
89 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) in am35x_musb_phy_power()
102 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); in am35x_musb_phy_power()
114 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()
117 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()
122 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); in am35x_set_mode()
Dpdata-quirks.c77 reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); in omap3_gpio126_127_129()
82 reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); in omap3_gpio126_127_129()
92 reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); in hsmmc2_internal_input_clk()
169 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()
173 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ in am35xx_enable_emac_int()
180 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()
183 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ in am35xx_disable_emac_int()
195 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35xx_emac_reset()
198 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ in am35xx_emac_reset()
Did.c58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); in omap_type()
60 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); in omap_type()
62 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); in omap_type()
64 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); in omap_type()
66 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); in omap_type()
68 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); in omap_type()
282 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); in omap3xxx_check_features()
341 status = omap_ctrl_readl(AM33XX_DEV_FEATURE); in am33xx_check_features()
Dtimer.c101 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); in realtime_counter_init()
Dcontrol.h510 extern u32 omap_ctrl_readl(u16 offset);
535 #define omap_ctrl_readl(x) 0 macro
Dpm24xx.c83 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; in omap2_enter_full_retention()
Dsr_device.c63 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); in sr_set_nvalues()
Dpm34xx.c78 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), in omap3_core_save_context()