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Searched refs:op2 (Results 1 – 25 of 25) sorted by relevance

/arch/arc/include/asm/
Datomic64-arcv2.h49 #define ATOMIC64_OP(op, op1, op2) \ argument
58 " " #op2 " %H0, %H0, %H2 \n" \
66 #define ATOMIC64_OP_RETURN(op, op1, op2) \ argument
75 " " #op2 " %H0, %H0, %H2 \n" \
88 #define ATOMIC64_FETCH_OP(op, op1, op2) \ argument
97 " " #op2 " %H1, %H0, %H3 \n" \
115 #define ATOMIC64_OPS(op, op1, op2) \ argument
116 ATOMIC64_OP(op, op1, op2) \
117 ATOMIC64_OP_RETURN(op, op1, op2) \
118 ATOMIC64_FETCH_OP(op, op1, op2)
[all …]
/arch/arm/include/asm/
Datomic.h304 #define ATOMIC64_OP(op, op1, op2) \ argument
314 " " #op2 " %R0, %R0, %R4\n" \
323 #define ATOMIC64_OP_RETURN(op, op1, op2) \ argument
335 " " #op2 " %R0, %R0, %R4\n" \
346 #define ATOMIC64_FETCH_OP(op, op1, op2) \ argument
358 " " #op2 " %R1, %R0, %R5\n" \
369 #define ATOMIC64_OPS(op, op1, op2) \ argument
370 ATOMIC64_OP(op, op1, op2) \
371 ATOMIC64_OP_RETURN(op, op1, op2) \
372 ATOMIC64_FETCH_OP(op, op1, op2)
[all …]
/arch/sh/kernel/
Dkprobes.c149 struct kprobe *op1, *op2; in prepare_singlestep() local
154 op2 = this_cpu_ptr(&saved_next_opcode2); in prepare_singlestep()
178 op2->addr = in prepare_singlestep()
180 op2->opcode = *(op2->addr); in prepare_singlestep()
181 arch_arm_kprobe(op2); in prepare_singlestep()
188 op2->addr = in prepare_singlestep()
190 op2->opcode = *(op2->addr); in prepare_singlestep()
191 arch_arm_kprobe(op2); in prepare_singlestep()
/arch/sparc/kernel/
Duprobes.c60 u32 op2 = (insn >> 22) & 0x7; in arch_uprobe_copy_ixol() local
63 (op2 == 1 || op2 == 2 || op2 == 3 || op2 == 5 || op2 == 6) && in arch_uprobe_copy_ixol()
/arch/arm64/crypto/
Dpolyval-ce-glue.c46 asmlinkage void pmull_polyval_mul(u8 *op1, const u8 *op2);
61 static void internal_polyval_mul(u8 *op1, const u8 *op2) in internal_polyval_mul() argument
65 pmull_polyval_mul(op1, op2); in internal_polyval_mul()
68 polyval_mul_non4k(op1, op2); in internal_polyval_mul()
/arch/x86/crypto/
Dcast6-avx-x86_64-asm_64.S85 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument
94 op2 s3(, RID1, 4), dst ## d; \
111 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument
112 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
113 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
115 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
118 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
130 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
Dpolyval-clmulni_glue.c50 asmlinkage void clmul_polyval_mul(u8 *op1, const u8 *op2);
70 static void internal_polyval_mul(u8 *op1, const u8 *op2) in internal_polyval_mul() argument
74 clmul_polyval_mul(op1, op2); in internal_polyval_mul()
77 polyval_mul_non4k(op1, op2); in internal_polyval_mul()
Dcast5-avx-x86_64-asm_64.S85 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument
94 op2 s3(, RID1, 4), dst ## d; \
111 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument
112 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
113 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
115 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
118 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
130 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
Dtwofish-x86_64-asm_64-3way.S77 #define do16bit_ror(rot, op1, op2, T0, T1, tmp1, tmp2, ab, dst) \ argument
82 op2##l T1(CTX, tmp1, 4), dst ## d;
/arch/x86/kvm/svm/
Dsvm_ops.h29 #define svm_asm2(insn, op1, op2, clobber...) \ argument
33 :: op1, op2 : clobber : fault); \
/arch/powerpc/math-emu/
Dmath.c28 #define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \
228 void *op0 = NULL, *op1 = NULL, *op2 = NULL, *op3 = NULL; in do_mathemu() local
334 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu()
340 op2 = (void *)&current->thread.TS_FPR((insn >> 6) & 0x1f); in do_mathemu()
346 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu()
400 op2 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu()
407 op2 = (void *)((insn >> 18) & 0x7); in do_mathemu()
435 eflag = func(op0, op1, op2, op3); in do_mathemu()
/arch/arm64/include/asm/
Desr.h181 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument
184 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
290 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ argument
292 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
Dsysreg.h37 #define sys_reg(op0, op1, crn, crm, op2) \ argument
40 ((op2) << Op2_shift))
89 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) argument
106 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ argument
107 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
483 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/arch/s390/net/
Dbpf_jit_comp.c199 #define _EMIT6(op1, op2) \ argument
203 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
208 #define _EMIT6_DISP(op1, op2, disp) \ argument
211 _EMIT6((op1) | __disp, op2); \
214 #define _EMIT6_DISP_LH(op1, op2, disp) \ argument
219 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
222 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ argument
225 reg_high(b3) << 8, op2, disp); \
231 #define EMIT6_PCREL_RIEB(op1, op2, b1, b2, mask, target) \ argument
235 (op2) | (mask) << 12); \
[all …]
/arch/arm64/include/uapi/asm/
Dkvm.h231 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
237 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
/arch/s390/include/asm/
Dpercpu.h66 #define arch_this_cpu_add(pcp, val, op1, op2, szcast) \ argument
76 op2 " %[ptr__],%[val__]\n" \
/arch/x86/kvm/vmx/
Dvmx_ops.h159 #define vmx_asm2(insn, op1, op2, error_args...) \ argument
165 : : op1, op2 : "cc" : error, fault); \
/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c323 #define ID_UNALLOCATED(crm, op2) { \ argument
324 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
/arch/x86/kernel/
Dalternative.c486 u8 op1, op2; in apply_retpolines() local
493 op2 = insn.opcode.bytes[1]; in apply_retpolines()
501 if (op2 >= 0x80 && op2 <= 0x8f) in apply_retpolines()
/arch/arm/include/asm/hardware/
Dcp14.h17 #define MRC14(op1, crn, crm, op2) \ argument
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
/arch/s390/kvm/
Dpriv.c90 u64 op2; in handle_set_clock() local
97 op2 = kvm_s390_get_base_disp_s(vcpu, &ar); in handle_set_clock()
98 if (op2 & 7) /* Operand must be on a doubleword boundary */ in handle_set_clock()
100 rc = read_guest(vcpu, op2, ar, &gtod.tod, sizeof(gtod.tod)); in handle_set_clock()
/arch/mips/kernel/
Dtraps.c719 int op2 = opcode & CSR_OPCODE2_MASK; in simulate_loongson3_cpucfg() local
722 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) { in simulate_loongson3_cpucfg()
/arch/m68k/fpsp040/
Dbugfix.S195 bne op2sgl |not opclass 0, check op2
/arch/arm64/kvm/
Dsys_regs.c1361 #define ID_UNALLOCATED(crm, op2) { \ argument
1362 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
/arch/m68k/ifpsp060/src/
Dfpsp.S15848 # FP_DST(a6) = fp op2(dst) #
15852 # FP_DST(a6) = fp op2 scaled(dst) #