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/arch/arm/boot/dts/
Dsama5d3_lcd.dtsi60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
Dexynos4412-pinctrl.dtsi3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
135 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
136 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
137 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
[all …]
Ds5pv210-pinctrl.dtsi24 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
25 samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
283 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
284 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
285 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
290 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
291 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
292 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
297 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
298 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
[all …]
Dexynos4210-pinctrl.dtsi3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
156 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
161 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
162 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
Dat91sam9x5_lcd.dtsi63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
Dexynos5420-pinctrl.dtsi3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
72 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
162 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
163 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
Dexynos5260-pinctrl.dtsi3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
210 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
215 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
216 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
Dexynos5250-pinctrl.dtsi3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
211 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
216 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
217 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
Dexynos3250-pinctrl.dtsi3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
25 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \
26 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \
27 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
33 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \
34 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \
[all …]
Ds3c64xx-pinctrl.dtsi4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
136 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
142 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
148 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
149 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
[all …]
Dexynos5410-pinctrl.dtsi3 * Exynos5410 SoC pin-mux and pin-config device tree source
282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
297 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
298 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
Ds3c2416-pinctrl.dtsi85 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
90 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
95 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
100 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
105 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
110 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
115 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
120 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
125 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
130 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
[all …]
Ds5pv210-aries.dtsi649 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
650 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
651 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
656 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
657 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
658 samsung,pin-val = <1>;
663 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
664 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
669 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
670 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
[all …]
/arch/arm64/boot/dts/exynos/
Dexynos5433-pinctrl.dtsi3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
134 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
135 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
136 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
141 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
142 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
Dexynos7-pinctrl.dtsi3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
191 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
198 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
203 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
204 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
/arch/arm/mach-orion5x/
Dboard-rd88f5182.c39 int pin; in rd88f5182_pci_preinit() local
44 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; in rd88f5182_pci_preinit()
45 if (gpio_request(pin, "PCI IntA") == 0) { in rd88f5182_pci_preinit()
46 if (gpio_direction_input(pin) == 0) { in rd88f5182_pci_preinit()
47 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in rd88f5182_pci_preinit()
50 "set_irq_type pin %d\n", pin); in rd88f5182_pci_preinit()
51 gpio_free(pin); in rd88f5182_pci_preinit()
54 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); in rd88f5182_pci_preinit()
57 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; in rd88f5182_pci_preinit()
58 if (gpio_request(pin, "PCI IntB") == 0) { in rd88f5182_pci_preinit()
[all …]
Drd88f5182-setup.c110 int pin; in rd88f5182_pci_preinit() local
115 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; in rd88f5182_pci_preinit()
116 if (gpio_request(pin, "PCI IntA") == 0) { in rd88f5182_pci_preinit()
117 if (gpio_direction_input(pin) == 0) { in rd88f5182_pci_preinit()
118 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in rd88f5182_pci_preinit()
121 "set_irq_type pin %d\n", pin); in rd88f5182_pci_preinit()
122 gpio_free(pin); in rd88f5182_pci_preinit()
125 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); in rd88f5182_pci_preinit()
128 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; in rd88f5182_pci_preinit()
129 if (gpio_request(pin, "PCI IntB") == 0) { in rd88f5182_pci_preinit()
[all …]
Dts209-setup.c107 int pin; in qnap_ts209_pci_preinit() local
112 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; in qnap_ts209_pci_preinit()
113 if (gpio_request(pin, "PCI Int1") == 0) { in qnap_ts209_pci_preinit()
114 if (gpio_direction_input(pin) == 0) { in qnap_ts209_pci_preinit()
115 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in qnap_ts209_pci_preinit()
118 "set_irq_type pin %d\n", pin); in qnap_ts209_pci_preinit()
119 gpio_free(pin); in qnap_ts209_pci_preinit()
123 "%d\n", pin); in qnap_ts209_pci_preinit()
126 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; in qnap_ts209_pci_preinit()
127 if (gpio_request(pin, "PCI Int2") == 0) { in qnap_ts209_pci_preinit()
[all …]
Ddb88f5281-setup.c204 int pin; in db88f5281_pci_preinit() local
209 pin = DB88F5281_PCI_SLOT0_IRQ_PIN; in db88f5281_pci_preinit()
210 if (gpio_request(pin, "PCI Int1") == 0) { in db88f5281_pci_preinit()
211 if (gpio_direction_input(pin) == 0) { in db88f5281_pci_preinit()
212 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in db88f5281_pci_preinit()
215 "set_irq_type pin %d\n", pin); in db88f5281_pci_preinit()
216 gpio_free(pin); in db88f5281_pci_preinit()
219 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); in db88f5281_pci_preinit()
222 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; in db88f5281_pci_preinit()
223 if (gpio_request(pin, "PCI Int2") == 0) { in db88f5281_pci_preinit()
[all …]
/arch/arm/mach-s3c/
Dpm-s3c24xx.c64 static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) in s3c_pm_check_resume_pin() argument
68 int irq = gpio_to_irq(pin); in s3c_pm_check_resume_pin()
75 pinstate = s3c_gpio_getcfg(pin); in s3c_pm_check_resume_pin()
79 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); in s3c_pm_check_resume_pin()
82 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); in s3c_pm_check_resume_pin()
83 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); in s3c_pm_check_resume_pin()
95 int pin; in s3c_pm_configure_extint() local
102 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) { in s3c_pm_configure_extint()
103 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0)); in s3c_pm_configure_extint()
106 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) { in s3c_pm_configure_extint()
[all …]
/arch/arm64/boot/dts/actions/
Ds900-bubblegum-96.dts69 * NC = not connected (pin out but not routed from the chip to
71 * "[PER]" = pin is muxed for [peripheral] (not GPIO)
94 "GPIO-A", /* GPIO_0, LSEC pin 23 */
95 "GPIO-B", /* GPIO_1, LSEC pin 24 */
96 "GPIO-C", /* GPIO_2, LSEC pin 25 */
97 "GPIO-D", /* GPIO_3, LSEC pin 26 */
98 "GPIO-E", /* GPIO_4, LSEC pin 27 */
99 "GPIO-F", /* GPIO_5, LSEC pin 28 */
100 "GPIO-G", /* GPIO_6, LSEC pin 29 */
101 "GPIO-H", /* GPIO_7, LSEC pin 30 */
[all …]
/arch/arm/plat-orion/
Dgpio.c96 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) in __set_direction() argument
102 u |= 1 << pin; in __set_direction()
104 u &= ~(1 << pin); in __set_direction()
108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) in __set_level() argument
114 u |= 1 << pin; in __set_level()
116 u &= ~(1 << pin); in __set_level()
121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) in __set_blinking() argument
127 u |= 1 << pin; in __set_blinking()
129 u &= ~(1 << pin); in __set_blinking()
134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) in orion_gpio_is_valid() argument
[all …]
/arch/arm64/boot/dts/hisilicon/
Dhi3670-hikey970.dts76 * NC = not connected (pin out but not routed from the chip to
78 * "[PER]" = pin is muxed for [peripheral] (not GPIO)
80 * unrouted (not connected to any external pin)
114 "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */
115 "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */
116 "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */
117 "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */
119 "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */
127 "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */
128 "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
[all …]
/arch/x86/kernel/apic/
Dio_apic.c73 #define for_each_pin(idx, pin) \ argument
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75 #define for_each_ioapic_pin(idx, pin) \ argument
77 for_each_pin((idx), (pin))
88 int apic, pin; member
147 static inline u32 mp_pin_to_gsi(int ioapic, int pin) in mp_pin_to_gsi() argument
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
289 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) in __ioapic_read_entry() argument
293 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin); in __ioapic_read_entry()
294 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin); in __ioapic_read_entry()
[all …]
/arch/arm64/boot/dts/bitmain/
Dbm1880-sophon-edge.dts13 * NC = not connected (pin out but not routed from the chip to
15 * "[PER]" = pin is muxed for [peripheral] (not GPIO)
56 "GPIO-A", /* GPIO0, LSEC pin 23 */
57 "GPIO-C", /* GPIO1, LSEC pin 25 */
59 "GPIO-E", /* GPIO3, LSEC pin 27 */
63 "GPIO-G", /* GPIO7, LSEC pin 29 */
96 "[I2C0_SDA]", /* GPIO34, LSEC pin 17 */
97 "[I2C0_SCL]", /* GPIO35, LSEC pin 15 */
112 "GPIO-I", /* GPIO50, LSEC pin 31 */
113 "GPIO-K", /* GPIO51, LSEC pin 33 */
[all …]

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