| /arch/powerpc/kernel/ |
| D | head_8xx.S | 192 mtspr SPRN_SPRG_SCRATCH2, r10
198 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
199 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
200 mtspr SPRN_MD_EPN, r10
203 compare_to_kernel_boundary r10, r10
205 mfspr r10, SPRN_M_TWB /* Get level 1 table */
208 rlwinm r10, r10, 0, 20, 31
209 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
213 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
215 mfspr r10, SPRN_MD_TWC
[all …]
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| D | head_32.h | 20 mtspr SPRN_SPRG_SCRATCH0,r10
22 mfspr r10, SPRN_SPRG_THREAD
29 stw r11, DAR(r10)
35 stw r11, DSISR(r10)
38 stw r11, SRR0(r10)
40 stw r11, SRR1(r10)
41 mfcr r10
80 stw r10,_CCR(r11) /* save registers */
83 mfspr r10,SPRN_SPRG_SCRATCH0
85 stw r10,GPR10(r11)
[all …]
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| D | head_booke.h | 48 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
49 mfspr r10, SPRN_SPRG_THREAD; \
50 stw r11, THREAD_NORMSAVE(0)(r10); \
51 stw r13, THREAD_NORMSAVE(2)(r10); \
62 lwz r11, TASK_STACK - THREAD(r10); \
70 lwz r12, THREAD_NORMSAVE(0)(r10); \
72 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
73 mflr r10; \
74 stw r10,_LINK(r11); \
85 lis r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
[all …]
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| D | exceptions-64s.S | 224 lbz r10,HSTATE_IN_GUEST(r13)
225 cmpwi r10,0
229 li r10,(IVEC + 0x2)
231 li r10,(IVEC)
234 li r10,(IVEC + 0x2)
236 li r10,(IVEC)
265 LOAD_HANDLER(r10, \name\()_common)
266 mtctr r10
273 LOAD_HANDLER(r10, \name\()_common_virt)
274 mtctr r10
[all …]
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| D | exceptions-64e.S | 84 mfspr r10,SPRN_SPRG_TLB_EXFRAME
85 add r10,r10,r12
86 mtspr SPRN_SPRG_TLB_EXFRAME,r10
92 mfspr r10,SPRN_SRR0
93 SPECIAL_EXC_STORE(r10,SRR0)
94 mfspr r10,SPRN_SRR1
95 SPECIAL_EXC_STORE(r10,SRR1)
96 mfspr r10,SPRN_SPRG_GEN_SCRATCH
97 SPECIAL_EXC_STORE(r10,SPRG_GEN)
98 mfspr r10,SPRN_SPRG_TLB_SCRATCH
[all …]
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| D | head_fsl_booke.S | 309 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
315 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
316 xor r12, r10, r11; /* drop size bits from pointer */ \
318 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
319 li r10, 0; /* clear r10 */ \
323 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
327 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
332 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
336 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
371 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
[all …]
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| D | idle_book3e.S | 63 ld r10,TI_LOCAL_FLAGS(r11)
64 ori r10,r10,_TLF_NAPPING
65 std r10,TI_LOCAL_FLAGS(r11)
72 lbz r10,PACAIRQHAPPENED(r13)
73 ori r10,r10,PACA_IRQ_HARD_DIS
74 stb r10,PACAIRQHAPPENED(r13)
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| D | head_40x.S | 109 stw r10,crit_r10@l(0) /* save two registers to work with */
111 mfspr r10,SPRN_SRR0
113 stw r10,crit_srr0@l(0)
115 mfspr r10,SPRN_DEAR
117 stw r10,crit_dear@l(0)
119 mfcr r10 /* save CR in r10 for now */
144 stw r10,_CCR(r11) /* save various registers */
147 mflr r10
148 stw r10,_LINK(r11)
150 lwz r10,crit_r10@l(r9)
[all …]
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| D | cpu_setup_fsl_booke.S | 97 mfspr r10,SPRN_MMUCFG
98 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
167 mfspr r10,SPRN_MMUCFG
168 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
190 mfspr r10,SPRN_MMUCFG
191 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
210 mfspr r10,SPRN_MMUCFG
211 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
216 ld r10,CPU_SPEC_FEATURES(r4)
218 andc r10,r10,r9
[all …]
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| D | head_book3s_32.S | 283 mtspr SPRN_SPRG_SCRATCH2,r10
284 mfspr r10, SPRN_SPRG_THREAD
285 stw r11, THR11(r10)
286 mfspr r10, SPRN_DSISR
288 andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
289 mfspr r10, SPRN_SPRG_THREAD
293 lwz r11, THR11(r10)
294 mfspr r10, SPRN_SPRG_SCRATCH2
315 mtspr SPRN_SPRG_SCRATCH0,r10
317 mfspr r10, SPRN_SPRG_THREAD
[all …]
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| /arch/powerpc/mm/nohash/ |
| D | tlb_low_64e.S | 47 std r10,EX_TLB_R10(r12)
50 mfcr r10
63 std r10,EX_TLB_CR(r12)
67 andi. r10,r11,MSR_PR
69 BTB_FLUSH(r10)
81 ld r10,EX_TLB_R10(r12)
120 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
123 rlwinm r10,r11,32-19,27,27
124 rlwimi r10,r11,32-16,19,19
126 ori r10,r10,_PAGE_PRESENT
[all …]
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| D | tlb_low.S | 74 mfmsr r10
108 10: wrtee r10
135 lis r10,tlb_47x_boltmap@h
136 ori r10,r10,tlb_47x_boltmap@l
165 lwz r8,0(r10) /* Load boltmap entry */
166 addi r10,r10,4 /* Next word */
182 mfmsr r10
195 wrtee r10
220 wrtee r10
253 mfmsr r10
[all …]
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| /arch/arm/crypto/ |
| D | sha1-armv4-large.S | 82 ldrb r10,[r1,#2]
87 orr r9,r9,r10,lsl#8
88 eor r10,r5,r6 @ F_xx_xx
95 eor r10,r5,r6 @ F_xx_xx
101 and r10,r4,r10,ror#2
103 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
105 add r7,r7,r10 @ E+=F_00_19(B,C,D)
107 ldrb r10,[r1,#2]
112 orr r9,r9,r10,lsl#8
113 eor r10,r4,r5 @ F_xx_xx
[all …]
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| /arch/powerpc/kvm/ |
| D | book3s_64_entry.S | 38 lbz r10,HSTATE_IN_GUEST(r13)
39 cmpwi r10,KVM_GUEST_MODE_HV_P9
42 ld r10,PACA_EXGEN+EX_R13(r13)
43 SET_SCRATCH0(r10)
44 li r10,0xc00
69 std r10,HSTATE_SCRATCH0(r13)
70 lbz r10,HSTATE_IN_GUEST(r13)
71 cmpwi r10,KVM_GUEST_MODE_HV_P9
73 ld r10,HSTATE_SCRATCH0(r13)
76 cmpdi r10,0x200
[all …]
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| D | book3s_64_slb.S | 50 li r10, 0
51 slbmte r10, r10
67 ld r10, 0(r11)
69 andis. r9, r10, SLB_ESID_V@h
73 slbmte r9, r10
131 LDX_BE r10, r11, r8
132 cmpdi r10, 0
135 slbmte r9, r10
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| /arch/powerpc/boot/ |
| D | crt0.S | 54 p_base: mflr r10 /* r10 now points to runtime addr of p_base */
57 addis r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha
63 addis r12,r10,(__dynamic_start-p_base)@ha
109 3: lwz r9,p_start-p_base(r10) /* note: these are relocated now */
110 lwz r8,p_etext-p_base(r10)
120 lwz r9,p_bss_start-p_base(r10)
121 lwz r8,p_end-p_base(r10)
129 lwz r8,p_pstack-p_base(r10)
138 std r5,(p_prom-p_base)(r10)
141 ld r2,(p_toc-p_base)(r10)
[all …]
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| /arch/powerpc/platforms/52xx/ |
| D | mpc52xx_sleep.S | 18 li r10, 0 /* flag that irq handler sets */
34 cmpi cr0, r10, 1
38 mfspr r10, SPRN_HID0
39 ori r10, r10, 0x2000
41 mtspr SPRN_HID0, r10
54 mfspr r10, SPRN_HID0
55 ori r10, r10, 0x2000
56 xori r10, r10, 0x2000
58 mtspr SPRN_HID0, r10
98 mfmsr r10
[all …]
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| D | lite5200_sleep.S | 24 mfspr r10, SPRN_##reg; \
25 stw r10, ((addr)*4)(r4);
28 lwz r10, ((addr)*4)(r4); \
29 mtspr SPRN_##reg, r10; \
65 lwz r10, 0xf0(r3)
66 stw r10, (0x1d*4)(r4)
206 mfmsr r10
207 ori r10, r10, MSR_DR | MSR_IR
210 mtspr SPRN_SRR1, r10
211 lis r10, mmu_on@h
[all …]
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| /arch/arm/mach-omap1/ |
| D | ams-delta-fiq-handler.S | 101 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
106 cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
110 orr r8, r11, r8, lsl r10 @ mask spurious interrupt
132 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
138 @ r10 now contains KEYBRD_CLK_MASK, use it
139 bic r11, r11, r10 @ unmask it
145 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
146 cmp r10, #0 @ are we expecting start bit?
154 @ r10 already contains 0, reuse it
155 str r10, [r9, #BUF_KEY] @ clear keycode
[all …]
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| /arch/parisc/kernel/ |
| D | head.S | 74 ldi 32,%r10
75 mtctl %r10,%cr11
77 mfctl,w %cr11,%r10
79 comib,<>,n 0,%r10,$cpu_ok
84 copy %arg0, %r10
95 stw %r10,-60(%sp) // arg6 = ptr to text
103 or %r10,%r10,%r10 /* qemu idle sleep */
177 load32 PA(_mcount), %r10
178 std %dp,0x18(%r10)
186 ldw MEM_PDC_HI(%r0),%r10
[all …]
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| /arch/arm/mach-imx/ |
| D | ssi-fiq.S | 57 mov r10, #0x10000
58 sub r10, #1
59 and r10, r10, r8 /* r10: current buffer offset */
61 add r13, r13, r10
75 add r10, #8
77 cmp r10, r11
95 mov r10, #0x10000
96 sub r10, #1
97 and r10, r10, r9 /* r10: current buffer offset */
99 add r13, r13, r10
[all …]
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| /arch/csky/kernel/ |
| D | entry.S | 66 bmaski r10, THREAD_SHIFT
67 andn r9, r10
68 ldw r10, (r9, TINFO_FLAGS)
70 and r10, r9
71 cmpnei r10, 0
126 mov a0, r10
133 bmaski r10, THREAD_SHIFT
134 andn r9, r10
135 ldw r10, (r9, TINFO_FLAGS)
137 and r10, r9
[all …]
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| /arch/arm/boot/bootp/ |
| D | init.S | 37 ldr r10, [r9, #4] @ get first tag
38 teq r10, r5 @ is it ATAG_CORE?
42 movne r10, #0 @ terminator
44 stmiane r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator
51 taglist: ldr r10, [r9, #0] @ tag length
52 teq r10, #0 @ last tag (zero length)?
53 addne r9, r9, r10, lsl #2
57 stmia r9, {r5, r6, r7, r8, r10}
63 move: ldmia r4!, {r7 - r10} @ move 32-bytes at a time
64 stmia r5!, {r7 - r10}
[all …]
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| /arch/arm/vfp/ |
| D | entry.S | 20 @ r10 = this threads thread_info structure
25 inc_preempt_count r10, r4
27 ldr r11, [r10, #TI_CPU] @ CPU number
28 add r10, r10, #TI_VFPSTATE @ r10 = workspace
33 dec_preempt_count_ti r10, r4
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| /arch/arc/include/asm/ |
| D | entry-arcv2.h | 85 ; _HARD saves r10 clobbered by _SOFT as scratch hence comes first
92 lr r10, [eret] variable
94 ST2 r10, r11, PT_ret
96 lr r10, [ecr]
98 ST2 r10, r11, PT_event
100 ; OUTPUT: r10 has ECR expected by EV_Trap
116 ST2 r10, r11, PT_r10
120 lr r10, [lp_end]
122 ST2 r10, r11, PT_lpe
152 lr r10, [AUX_USER_SP] ; U mode SP
[all …]
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