| /arch/x86/kernel/cpu/mce/ |
| D | p5.c | 29 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); in pentium_machine_check()
30 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); in pentium_machine_check()
62 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); in intel_p5_mcheck_init()
63 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); in intel_p5_mcheck_init()
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| D | winchip.c | 37 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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| /arch/x86/kernel/cpu/mtrr/ |
| D | generic.c | 56 rdmsr(MSR_AMD64_SYSCFG, lo, hi); in k8_check_syscfg_dram_mod_en()
317 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); in get_mtrr_var_range()
318 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); in get_mtrr_var_range()
342 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); in get_fixed_ranges()
345 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); in get_fixed_ranges()
347 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); in get_fixed_ranges()
470 rdmsr(MSR_MTRRcap, lo, dummy); in get_mtrr_state()
478 rdmsr(MSR_MTRRdefType, lo, dummy); in get_mtrr_state()
486 rdmsr(MSR_K8_TOP_MEM2, low, high); in get_mtrr_state()
542 rdmsr(msr, lo, hi); in set_fixed_range()
[all …]
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| D | amd.c | 15 rdmsr(MSR_K6_UWCCR, low, high); in amd_get_mtrr()
67 rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
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| /arch/x86/kernel/ |
| D | tsc_msr.c | 181 rdmsr(MSR_PLATFORM_INFO, lo, hi); in cpu_khz_from_msr()
184 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in cpu_khz_from_msr()
189 rdmsr(MSR_FSB_FREQ, lo, hi); in cpu_khz_from_msr()
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| D | verify_cpu.S | 94 rdmsr
126 rdmsr
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| D | head_32.S | 243 rdmsr
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| /arch/x86/kernel/cpu/ |
| D | centaur.c | 32 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
40 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
54 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
184 rdmsr(MSR_IDT_FCR1, lo, hi); in init_centaur()
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| D | zhaoxin.c | 30 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
39 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
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| D | feat_ctl.c | 39 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported); in init_vmx_capabilities()
45 rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported); in init_vmx_capabilities()
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| D | transmeta.c | 86 rdmsr(0x80860004, cap_mask, uk); in init_transmeta()
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| D | amd.c | 243 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
264 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
311 rdmsr(MSR_K7_CLK_CTL, l, h); in init_amd_k7()
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| /arch/x86/boot/compressed/ |
| D | mem_encrypt.S | 43 rdmsr
80 rdmsr
209 rdmsr
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| D | efi_thunk_64.S | 124 rdmsr
152 rdmsr
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| D | head_64.S | 242 rdmsr
660 rdmsr
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| /arch/x86/mm/ |
| D | mem_encrypt_boot.S | 117 rdmsr
150 rdmsr
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| /arch/x86/hyperv/ |
| D | hv_apic.c | 62 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
66 rdmsr(HV_X64_MSR_TPR, reg_val, hi); in hv_apic_read()
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| /arch/x86/lib/ |
| D | msr-reg.S | 91 op_safe_regs rdmsr
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| D | msr-smp.c | 19 rdmsr(rv->msr_no, reg->l, reg->h); in __rdmsr_on_cpu()
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| /arch/x86/platform/pvh/ |
| D | head.S | 80 rdmsr
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| /arch/x86/include/asm/ |
| D | msr.h | 254 #define rdmsr(msr, low, high) \ macro
338 rdmsr(msr_no, *l, *h); in rdmsr_on_cpu()
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| /arch/x86/realmode/rm/ |
| D | trampoline_64.S | 127 rdmsr
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| /arch/x86/entry/ |
| D | calling.h | 304 rdmsr
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| /arch/x86/kernel/apic/ |
| D | apic.c | 1234 rdmsr(MSR_IA32_APICBASE, l, h); in disable_local_APIC()
1982 rdmsr(MSR_IA32_APICBASE, l, h); in apic_verify()
2004 rdmsr(MSR_IA32_APICBASE, l, h); in apic_force_enable()
2724 rdmsr(MSR_IA32_APICBASE, l, h); in lapic_resume()
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| /arch/x86/kernel/cpu/microcode/ |
| D | amd.c | 584 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); in reload_ucode_amd()
699 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); in apply_microcode_amd()
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