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Searched refs:readl_relaxed (Results 1 – 25 of 96) sorted by relevance

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/arch/arm/mach-mv78xx0/
Dirq.c31 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF); in mv78xx0_legacy_handle_irq()
32 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF); in mv78xx0_legacy_handle_irq()
38 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF); in mv78xx0_legacy_handle_irq()
39 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF); in mv78xx0_legacy_handle_irq()
45 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF); in mv78xx0_legacy_handle_irq()
46 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF); in mv78xx0_legacy_handle_irq()
/arch/arm/mach-dove/
Dirq.c47 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); in dove_legacy_handle_irq()
48 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); in dove_legacy_handle_irq()
54 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); in dove_legacy_handle_irq()
55 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); in dove_legacy_handle_irq()
/arch/arm/mach-hisi/
Dhotplug.c105 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
115 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
201 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
206 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
211 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
217 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
238 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
245 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
Dplatmcpm.c87 data = readl_relaxed(fabric + FAB_SF_MODE); in hip04_set_snoop_filter()
95 } while (data != readl_relaxed(fabric + FAB_SF_MODE)); in hip04_set_snoop_filter()
125 data = readl_relaxed(sys_status); in hip04_boot_secondary()
135 } while (data == readl_relaxed(sys_status)); in hip04_boot_secondary()
208 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); in hip04_cpu_kill()
223 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); in hip04_cpu_kill()
/arch/arm/mach-vexpress/
Ddcscb.c47 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerup()
62 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerup()
76 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerdown_prepare()
88 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerdown_prepare()
150 cfg = readl_relaxed(dcscb_base + DCS_CFG_R); in dcscb_init()
Dtc2_pm.c120 return !(readl_relaxed(scc + RESET_CTRL) & mask); in tc2_core_in_reset()
136 readl_relaxed(scc + RESET_CTRL)); in tc2_pm_wait_for_powerdown()
220 a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; in tc2_pm_init()
221 a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; in tc2_pm_init()
225 sys_info = readl_relaxed(scc + SYS_INFO); in tc2_pm_init()
/arch/arm/mach-omap2/
Domap4-common.c119 writel_relaxed(readl_relaxed(dram_sync), dram_sync); in omap_interconnect_sync()
120 writel_relaxed(readl_relaxed(sram_sync), sram_sync); in omap_interconnect_sync()
188 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); in gic_dist_disabled()
193 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
194 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); in gic_timer_retrigger()
195 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
Domap-wakeupgen.c77 return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 + in wakeupgen_readl()
264 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap4_irq_save_context()
266 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); in omap4_irq_save_context()
270 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); in omap4_irq_save_context()
272 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN); in omap4_irq_save_context()
276 val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); in omap4_irq_save_context()
297 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap5_irq_save_context()
299 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap5_irq_save_context()
303 val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); in omap5_irq_save_context()
351 val = readl_relaxed(sar_base + offset); in irq_sar_clear()
Dwd_timer.c49 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) in omap2_wd_timer_disable()
53 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) in omap2_wd_timer_disable()
/arch/arm/common/
Dsa1111.c211 stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0); in sa1111_irq_handler()
212 stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1); in sa1111_irq_handler()
259 ie = readl_relaxed(mapbase + SA1111_INTEN0); in sa1111_mask_irq()
270 ie = readl_relaxed(mapbase + SA1111_INTEN0); in sa1111_unmask_irq()
289 ip = readl_relaxed(mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
293 if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask) in sa1111_retrigger_irq()
318 ip = readl_relaxed(mapbase + SA1111_INTPOL0); in sa1111_type_irq()
335 we = readl_relaxed(mapbase + SA1111_WAKEEN0); in sa1111_wake_irq()
506 val = readl_relaxed(reg); in sa1111_gpio_modify()
518 return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask); in sa1111_gpio_get_direction()
[all …]
/arch/arm/plat-omap/
Dcounter_32k.c40 return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_32k_read_sched_clock()
60 cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_read_persistent_clock64()
89 if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & in omap_init_clocksource_32k()
/arch/arm/mach-sa1100/include/mach/
Dmtd-xip.h20 #define xip_currtime() readl_relaxed(OSCR)
21 #define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
/arch/arm/mach-s3c/
Dcpu.c20 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118); in s3c64xx_init_cpu()
27 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
Dpm-common.c30 ptr->val = readl_relaxed(ptr->reg); in s3c_pm_do_save()
50 ptr->reg, ptr->val, readl_relaxed(ptr->reg)); in s3c_pm_do_restore()
/arch/arm/mach-imx/
Dsrc.c66 val = readl_relaxed(src_base + SRC_SCR); in imx_src_reset_module()
106 val = readl_relaxed(gpc_base + reg); in imx_gpcv2_set_core1_pdn_pup_by_software()
133 val = readl_relaxed(src_base + SRC_A7RCR1); in imx_enable_cpu()
138 val = readl_relaxed(src_base + SRC_SCR); in imx_enable_cpu()
156 return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); in imx_get_cpu_arg()
181 val = readl_relaxed(src_base + SRC_SCR); in imx_src_init()
Dmach-vf610.c37 cpxcount = readl_relaxed(mscm + MSCM_CPxCOUNT); in vf610_detect_cpu()
38 cpxcfg1 = readl_relaxed(mscm + MSCM_CPxCFG1); in vf610_detect_cpu()
Dgpc.c55 val = readl_relaxed(gpc_base + GPC_CNTR); in imx_gpc_set_l2_mem_power_in_lpm()
72 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); in imx_gpc_pre_suspend()
111 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); in imx_gpc_mask_all()
131 val = readl_relaxed(reg); in imx_gpc_hwirq_unmask()
142 val = readl_relaxed(reg); in imx_gpc_hwirq_mask()
Dpm-imx6.c235 u32 val = readl_relaxed(ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
254 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
260 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
281 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()
287 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
295 u32 val = readl_relaxed(ccm_base + CLPCR); in imx6_set_lpm()
566 readl_relaxed(pm_info->iomuxc_base.vbase + in imx6q_suspend_init()
657 val = readl_relaxed(ccm_base + CLPCR); in imx6_pm_ccm_init()
/arch/arm/mach-omap1/
Dirq.c72 return readl_relaxed(irq_banks[bank].va + offset); in irq_bank_readl()
151 irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); in omap1_handle_irq()
152 irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); in omap1_handle_irq()
156 irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); in omap1_handle_irq()
160 irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); in omap1_handle_irq()
162 irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); in omap1_handle_irq()
/arch/arm/kernel/
Dsmp_scu.c31 unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG); in scu_get_core_count()
45 scu_ctrl = readl_relaxed(scu_base + 0x30); in scu_enable()
51 scu_ctrl = readl_relaxed(scu_base + SCU_CTRL); in scu_enable()
/arch/arm/mach-orion5x/
Dirq.c31 stat = readl_relaxed(MAIN_IRQ_CAUSE); in orion5x_legacy_handle_irq()
32 stat &= readl_relaxed(MAIN_IRQ_MASK); in orion5x_legacy_handle_irq()
/arch/arm/mm/
Dcache-l2x0.c57 while (readl_relaxed(reg) & mask) in l2c_wait_mask()
67 if (val == readl_relaxed(base + reg)) in l2c_write_sec()
145 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); in l2c_save()
153 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) in l2c_resume()
400 if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN) in l2c220_unlock()
545 l2x0_saved_regs.tag_latency = readl_relaxed(base + in l2c310_save()
547 l2x0_saved_regs.data_latency = readl_relaxed(base + in l2c310_save()
549 l2x0_saved_regs.filter_end = readl_relaxed(base + in l2c310_save()
551 l2x0_saved_regs.filter_start = readl_relaxed(base + in l2c310_save()
554 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_save()
[all …]
/arch/riscv/include/asm/
Dtimex.h25 return readl_relaxed(((u32 *)clint_time_val)); in get_cycles()
31 return readl_relaxed(((u32 *)clint_time_val) + 1); in get_cycles_hi()
/arch/arm/mach-ux500/
Dpm.c96 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); in prcmu_gic_pending_irq()
97 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in prcmu_gic_pending_irq()
149 er = readl_relaxed(dist_base + in prcmu_copy_gic_settings()
/arch/arm/mach-mmp/
Ddevices.c82 return readl_relaxed(base + offset); in u2o_get()
90 reg = readl_relaxed(base + offset); in u2o_set()
93 readl_relaxed(base + offset); in u2o_set()
101 reg = readl_relaxed(base + offset); in u2o_clear()
104 readl_relaxed(base + offset); in u2o_clear()
111 readl_relaxed(base + offset); in u2o_write()

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