| /arch/parisc/include/asm/ |
| D | asmregs.h | 11 rp: .reg %r2
12 arg3: .reg %r23
13 arg2: .reg %r24
14 arg1: .reg %r25
15 arg0: .reg %r26
16 dp: .reg %r27
17 ret0: .reg %r28
18 ret1: .reg %r29
19 sl: .reg %r29
20 sp: .reg %r30
[all …]
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| /arch/mips/include/asm/ |
| D | asm-eva.h | 19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument
20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument
21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument
22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument
23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument
24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument
25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument
26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument
27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument
28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument
[all …]
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-fau.h | 129 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) in __cvmx_fau_store_address() argument
133 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_store_address()
152 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, in __cvmx_fau_atomic_address() argument
158 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_atomic_address()
170 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, in cvmx_fau_fetch_and_add64() argument
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64()
185 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, in cvmx_fau_fetch_and_add32() argument
188 reg ^= SWIZZLE_32; in cvmx_fau_fetch_and_add32()
189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32()
200 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, in cvmx_fau_fetch_and_add16() argument
[all …]
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| /arch/ia64/include/asm/native/ |
| D | inst.h | 11 #define MOV_FROM_IFA(reg) \ argument
12 mov reg = cr.ifa
14 #define MOV_FROM_ITIR(reg) \ argument
15 mov reg = cr.itir
17 #define MOV_FROM_ISR(reg) \ argument
18 mov reg = cr.isr
20 #define MOV_FROM_IHA(reg) \ argument
21 mov reg = cr.iha
23 #define MOV_FROM_IPSR(pred, reg) \ argument
24 (pred) mov reg = cr.ipsr
[all …]
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| /arch/arm/boot/dts/ |
| D | aspeed-bmc-ibm-everest.dts | 143 reg = <0x80000000 0x40000000>;
154 reg = <0xb8000000 0x04000000>; /* 64M */
160 reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
171 reg = <0xbf000000 0x01000000>; /* 16M */
287 reg = <0x51>;
292 reg = <0x62>;
317 reg = <0>;
322 reg = <1>;
327 reg = <2>;
332 reg = <3>;
[all …]
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| D | ibm-power9-dual.dtsi | 6 reg = <0 0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
23 reg = <0>;
27 reg = <1>;
31 reg = <2>;
35 reg = <3>;
39 reg = <4>;
43 reg = <5>;
47 reg = <6>;
[all …]
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| D | aspeed-bmc-facebook-fuji.dts | 213 <0>, /* device reg=<1> does not exist */
221 reg = <2>;
240 reg = <0x70>;
246 reg = <0>;
250 reg = <0x10>;
260 reg = <1>;
266 reg = <2>;
272 reg = <3>;
278 reg = <4>;
284 reg = <5>;
[all …]
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| D | aspeed-bmc-facebook-cmm.dts | 335 reg = <0x77>;
342 reg = <0>;
348 reg = <0x70>;
354 reg = <0>;
359 reg = <1>;
364 reg = <2>;
369 reg = <3>;
374 reg = <4>;
379 reg = <5>;
384 reg = <6>;
[all …]
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| D | aspeed-bmc-ibm-rainier.dts | 90 reg = <0x80000000 0x40000000>;
100 reg = <0xb8000000 0x04000000>; /* 64M */
105 reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
115 reg = <0xbf000000 0x01000000>; /* 16M */
161 reg = <0>;
167 reg = <1>;
173 reg = <2>;
179 reg = <3>;
341 reg = <0 0>;
348 reg = <0x1000 0x400>;
[all …]
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| D | aspeed-bmc-opp-swift.dts | 17 reg = <0x80000000 0x20000000>;
27 reg = <0x98000000 0x04000000>; /* 64M */
235 reg = < 0 0x60000 >;
239 reg = < 0x60000 0x20000 >;
243 reg = < 0x80000 0x7F80000>;
259 reg = < 0 0x60000 >;
263 reg = < 0x60000 0x20000 >;
267 reg = < 0x80000 0x7F80000>;
342 reg = <0x52>;
348 reg = <0>;
[all …]
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| D | aspeed-bmc-facebook-cloudripper.dts | 90 reg = <1>;
113 reg = <0x0d>;
139 reg = <0x70>;
145 reg = <0>;
151 reg = <1>;
157 reg = <2>;
163 reg = <3>;
169 reg = <4>;
175 reg = <5>;
181 reg = <6>;
[all …]
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| D | aspeed-bmc-inspur-nf5280m6.dts | 20 reg = <0x80000000 0x40000000>;
30 reg = <0x9f000000 0x01000000>; /* 16M */
198 reg = <0x50>;
208 reg = <0x48>;
214 reg = <0x49>;
220 reg = <0x70>;
229 reg = <0x70>;
234 reg = <0x71>;
239 reg = <0x72>;
253 reg = <0x70>;
[all …]
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| D | aspeed-bmc-facebook-minipack.dts | 255 reg = <0x0 0x60000>;
263 reg = <0x60000 0x20000>;
271 reg = <0x80000 0x3780000>;
280 reg = <0x3800000 0x800000>;
289 reg = <0x0 0x4000000>;
302 reg = <0x0 0x4000000>;
351 reg = <0x70>;
357 reg = <0>;
363 reg = <1>;
369 reg = <2>;
[all …]
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| /arch/x86/include/asm/ |
| D | xor_avx.h | 37 #define BLOCK(i, reg) \ in xor_avx_2() argument
39 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \ in xor_avx_2()
40 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_2()
42 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ in xor_avx_2()
64 #define BLOCK(i, reg) \ in xor_avx_3() argument
66 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \ in xor_avx_3()
67 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3()
69 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3()
71 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ in xor_avx_3()
94 #define BLOCK(i, reg) \ in xor_avx_4() argument
[all …]
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| /arch/sh/include/mach-common/mach/ |
| D | magicpanelr2.h | 19 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) argument
20 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) argument
21 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) argument
22 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) argument
23 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) argument
24 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) argument
|
| /arch/m68k/math-emu/ |
| D | multi_arith.h | 21 static inline void fp_denormalize(struct fp_ext *reg, unsigned int cnt) in fp_denormalize() argument
23 reg->exp += cnt; in fp_denormalize()
27 reg->lowmant = reg->mant.m32[1] << (8 - cnt); in fp_denormalize()
28 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | in fp_denormalize()
29 (reg->mant.m32[0] << (32 - cnt)); in fp_denormalize()
30 reg->mant.m32[0] = reg->mant.m32[0] >> cnt; in fp_denormalize()
33 reg->lowmant = reg->mant.m32[1] >> (cnt - 8); in fp_denormalize()
34 if (reg->mant.m32[1] << (40 - cnt)) in fp_denormalize()
35 reg->lowmant |= 1; in fp_denormalize()
36 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | in fp_denormalize()
[all …]
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| /arch/arm/mach-cns3xxx/ |
| D | pm.c | 17 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en() local
19 reg |= (block & PM_CLK_GATE_REG_MASK); in cns3xxx_pwr_clk_en()
20 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
26 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis() local
28 reg &= ~(block & PM_CLK_GATE_REG_MASK); in cns3xxx_pwr_clk_dis()
29 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
35 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up() local
37 reg &= ~(block & CNS3XXX_PWR_PLL_ALL); in cns3xxx_pwr_power_up()
38 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
47 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down() local
[all …]
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| /arch/arm/mach-omap2/ |
| D | sdrc.h | 24 #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) argument
25 #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) argument
29 static inline void sdrc_write_reg(u32 val, u16 reg) in sdrc_write_reg() argument
31 writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); in sdrc_write_reg()
34 static inline u32 sdrc_read_reg(u16 reg) in sdrc_read_reg() argument
36 return readl_relaxed(OMAP_SDRC_REGADDR(reg)); in sdrc_read_reg()
41 static inline void sms_write_reg(u32 val, u16 reg) in sms_write_reg() argument
43 writel_relaxed(val, OMAP_SMS_REGADDR(reg)); in sms_write_reg()
46 static inline u32 sms_read_reg(u16 reg) in sms_read_reg() argument
48 return readl_relaxed(OMAP_SMS_REGADDR(reg)); in sms_read_reg()
[all …]
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| /arch/mips/pci/ |
| D | ops-sni.c | 24 static int set_config_address(unsigned int busno, unsigned int devfn, int reg) in set_config_address() argument
26 if ((devfn > 255) || (reg > 255)) in set_config_address()
35 (reg & 0xfc); in set_config_address()
40 static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg, in pcimt_read() argument
45 if ((res = set_config_address(bus->number, devfn, reg))) in pcimt_read()
50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); in pcimt_read()
53 *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); in pcimt_read()
63 static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, in pcimt_write() argument
68 if ((res = set_config_address(bus->number, devfn, reg))) in pcimt_write()
73 outb(val, PCIMT_CONFIG_DATA + (reg & 3)); in pcimt_write()
[all …]
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| /arch/arm/mach-sunxi/ |
| D | mc_smp.c | 119 u32 reg; in sunxi_cpu_power_switch_set() local
122 reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
124 if (reg == 0x00) { in sunxi_cpu_power_switch_set()
161 u32 reg; in sunxi_cpu_powerup() local
172 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
173 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu); in sunxi_cpu_powerup()
174 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
178 reg = readl(r_cpucfg_base + in sunxi_cpu_powerup()
180 reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu)); in sunxi_cpu_powerup()
181 writel(reg, r_cpucfg_base + in sunxi_cpu_powerup()
[all …]
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| /arch/arm64/kvm/hyp/include/hyp/ |
| D | debug-sr.h | 21 #define save_debug(ptr,reg,nr) \ argument
23 case 15: ptr[15] = read_debug(reg, 15); \
25 case 14: ptr[14] = read_debug(reg, 14); \
27 case 13: ptr[13] = read_debug(reg, 13); \
29 case 12: ptr[12] = read_debug(reg, 12); \
31 case 11: ptr[11] = read_debug(reg, 11); \
33 case 10: ptr[10] = read_debug(reg, 10); \
35 case 9: ptr[9] = read_debug(reg, 9); \
37 case 8: ptr[8] = read_debug(reg, 8); \
39 case 7: ptr[7] = read_debug(reg, 7); \
[all …]
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| /arch/mips/ath79/ |
| D | common.c | 56 void ath79_ddr_wb_flush(u32 reg) in ath79_ddr_wb_flush() argument
58 void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); in ath79_ddr_wb_flush()
90 u32 reg; in ath79_device_reset_set() local
94 reg = AR71XX_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
96 reg = AR724X_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
98 reg = AR913X_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
100 reg = AR933X_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
102 reg = AR934X_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
104 reg = QCA953X_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
106 reg = QCA955X_RESET_REG_RESET_MODULE; in ath79_device_reset_set()
[all …]
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| /arch/arm64/boot/dts/microchip/ |
| D | sparx5_pcb135_board.dtsi | 95 reg = <0>;
106 reg = <0>; /* CS0 */
110 reg = <0x9>; /* SPI */
150 reg = <0x0>;
155 reg = <0x1>;
160 reg = <0x2>;
165 reg = <0x3>;
213 reg = <0>;
216 reg = <1>;
219 reg = <2>;
[all …]
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| /arch/x86/pci/ |
| D | olpc.c | 179 static uint32_t *hdr_addr(const uint32_t *hdr, int reg) in hdr_addr() argument
194 addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20); in hdr_addr()
201 unsigned int devfn, int reg, int len, uint32_t *value) in pci_olpc_read() argument
209 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); in pci_olpc_read()
215 if (reg >= 0x70) in pci_olpc_read()
220 addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg); in pci_olpc_read()
223 addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg); in pci_olpc_read()
226 addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc; in pci_olpc_read()
229 addr = hdr_addr(isa_hdr, reg); in pci_olpc_read()
232 addr = hdr_addr(ac97_hdr, reg); in pci_olpc_read()
[all …]
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| /arch/mips/bcm63xx/ |
| D | timer.c | 59 u32 reg; in bcm63xx_timer_enable() local
67 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); in bcm63xx_timer_enable()
68 reg |= TIMER_CTL_ENABLE_MASK; in bcm63xx_timer_enable()
69 bcm_timer_writel(reg, TIMER_CTLx_REG(id)); in bcm63xx_timer_enable()
71 reg = bcm_timer_readl(TIMER_IRQSTAT_REG); in bcm63xx_timer_enable()
72 reg |= TIMER_IRQSTAT_TIMER_IR_EN(id); in bcm63xx_timer_enable()
73 bcm_timer_writel(reg, TIMER_IRQSTAT_REG); in bcm63xx_timer_enable()
83 u32 reg; in bcm63xx_timer_disable() local
91 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); in bcm63xx_timer_disable()
92 reg &= ~TIMER_CTL_ENABLE_MASK; in bcm63xx_timer_disable()
[all …]
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