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/arch/m68k/coldfire/
DMakefile19 obj-$(CONFIG_M5206) += m5206.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o intc-2.o reset.o
27 obj-$(CONFIG_M528x) += m528x.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o intc.o reset.o
29 obj-$(CONFIG_M53xx) += m53xx.o intc-simr.o reset.o
[all …]
/arch/arm/boot/dts/
Dmeson8m2.dtsi36 resets = <&reset RESET_ETHERNET>;
37 reset-names = "stmmaceth";
66 resets = <&reset RESET_DBLK>,
67 <&reset RESET_PIC_DC>,
68 <&reset RESET_HDMI_APB>,
69 <&reset RESET_HDMI_SYSTEM_RESET>,
70 <&reset RESET_VENCI>,
71 <&reset RESET_VENCP>,
72 <&reset RESET_VDAC_4>,
73 <&reset RESET_VENCL>,
[all …]
Drtd1195.dtsi11 #include <dt-bindings/reset/realtek,rtd1195.h>
164 reset1: reset-controller@0 {
165 compatible = "snps,dw-low-reset";
167 #reset-cells = <1>;
170 reset2: reset-controller@4 {
171 compatible = "snps,dw-low-reset";
173 #reset-cells = <1>;
176 reset3: reset-controller@8 {
177 compatible = "snps,dw-low-reset";
179 #reset-cells = <1>;
[all …]
Dtegra20.dtsi44 reset-names = "host1x";
57 reset-names = "mpe";
66 reset-names = "vi";
75 reset-names = "epp";
84 reset-names = "isp";
93 reset-names = "2d";
101 reset-names = "3d";
112 reset-names = "dc";
140 reset-names = "dc";
168 reset-names = "hdmi";
[all …]
Dbcm2711-rpi.dtsi4 #include <dt-bindings/reset/raspberrypi,firmware-reset.h>
34 reset: reset { label
35 compatible = "raspberrypi,firmware-reset";
36 #reset-cells = <1>;
Dtegra114.dtsi29 reset-names = "host1x";
43 reset-names = "2d";
53 reset-names = "3d";
66 reset-names = "dc";
85 reset-names = "dc";
104 reset-names = "hdmi";
116 reset-names = "dsi";
132 reset-names = "dsi";
182 #reset-cells = <1>;
227 reset-names = "dma";
[all …]
Duniphier-pxs2.dtsi273 reset-names = "aio";
431 sd_rst: reset {
432 compatible = "socionext,uniphier-pxs2-sd-reset";
433 #reset-cells = <1>;
447 peri_rst: reset {
448 compatible = "socionext,uniphier-pxs2-peri-reset";
449 #reset-cells = <1>;
461 reset-names = "host", "hw";
465 cap-mmc-hw-reset;
478 reset-names = "host";
[all …]
Duniphier-pro5.dtsi350 sd_rst: reset {
351 compatible = "socionext,uniphier-pro5-sd-reset";
352 #reset-cells = <1>;
366 peri_rst: reset {
367 compatible = "socionext,uniphier-pro5-peri-reset";
368 #reset-cells = <1>;
462 sys_rst: reset {
463 compatible = "socionext,uniphier-pro5-reset";
464 #reset-cells = <1>;
490 usb0_rst: reset@0 {
[all …]
Dtegra30.dtsi57 reset-names = "pex", "afi", "pcie_x";
125 reset-names = "host1x";
139 reset-names = "mpe";
150 reset-names = "vi";
161 reset-names = "epp";
172 reset-names = "isp";
183 reset-names = "2d";
196 reset-names = "3d", "3d2";
210 reset-names = "dc";
240 reset-names = "dc";
[all …]
Duniphier-pro4.dtsi252 mio_rst: reset {
253 compatible = "socionext,uniphier-pro4-mio-reset";
254 #reset-cells = <1>;
268 peri_rst: reset {
269 compatible = "socionext,uniphier-pro4-peri-reset";
270 #reset-cells = <1>;
293 reset-names = "host", "bridge";
312 reset-names = "host", "bridge", "hw";
318 cap-mmc-hw-reset;
330 reset-names = "host", "bridge";
[all …]
Dmeson8b.dtsi11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
273 resets = <&reset RESET_MALI>;
302 resets = <&reset RESET_AIU>;
390 resets = <&reset RESET_MEDIA_CPU>;
395 reset: reset-controller@4404 { label
396 compatible = "amlogic,meson8b-reset";
398 #reset-cells = <1>;
576 resets = <&reset RESET_ETHERNET>;
577 reset-names = "stmmaceth";
[all …]
Dtegra124.dtsi7 #include <dt-bindings/reset/tegra124-car.h>
57 reset-names = "pex", "afi", "pcie_x";
98 reset-names = "host1x";
113 reset-names = "dc";
140 reset-names = "dc";
164 reset-names = "hdmi";
175 reset-names = "vic";
191 reset-names = "sor";
203 reset-names = "dpaux";
242 reset-names = "gpu";
[all …]
Dast2500-facebook-netbmc-common.dtsi13 * Update reset type to "system" (full chip) to fix warm reboot hang issue
14 * when reset type is set to default ("soc", gated by reset mask registers).
18 aspeed,reset-type = "system";
/arch/arm64/boot/dts/realtek/
Drtd139x.dtsi12 #include <dt-bindings/reset/realtek,rtd1295.h>
124 reset1: reset-controller@0 {
125 compatible = "snps,dw-low-reset";
127 #reset-cells = <1>;
130 reset2: reset-controller@4 {
131 compatible = "snps,dw-low-reset";
133 #reset-cells = <1>;
136 reset3: reset-controller@8 {
137 compatible = "snps,dw-low-reset";
139 #reset-cells = <1>;
[all …]
Drtd129x.dtsi13 #include <dt-bindings/reset/realtek,rtd1295.h>
126 reset1: reset-controller@0 {
127 compatible = "snps,dw-low-reset";
129 #reset-cells = <1>;
132 reset2: reset-controller@4 {
133 compatible = "snps,dw-low-reset";
135 #reset-cells = <1>;
138 reset3: reset-controller@8 {
139 compatible = "snps,dw-low-reset";
141 #reset-cells = <1>;
[all …]
/arch/arm64/boot/dts/amlogic/
Dmeson-gxl.dtsi11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
27 resets = <&reset RESET_USB_OTG>;
64 resets = <&reset RESET_ACODEC>;
100 resets = <&reset RESET_AIU>;
110 resets = <&reset RESET_USB_OTG>;
111 reset-names = "phy";
121 resets = <&reset RESET_USB_OTG>;
122 reset-names = "phy";
322 resets = <&reset RESET_HDMITX_CAPB3>,
323 <&reset RESET_HDMI_SYSTEM_RESET>,
[all …]
Dmeson-gxbb.dtsi9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
22 resets = <&reset RESET_USB_OTG>;
32 resets = <&reset RESET_USB_OTG>;
84 resets = <&reset RESET_AIU>;
310 resets = <&reset RESET_HDMITX_CAPB3>,
311 <&reset RESET_HDMI_SYSTEM_RESET>,
312 <&reset RESET_HDMI_TX>;
313 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
723 resets = <&reset RESET_VIU>,
[all …]
Dmeson-gxbb-kii-pro.dts33 button-reset {
34 label = "reset";
73 reset-assert-us = <10000>;
74 reset-deassert-us = <10000>;
75 reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
Dmeson-gxbb-p201.dts23 snps,reset-gpio = <&gpio GPIOZ_14 0>;
24 snps,reset-delays-us = <0>, <10000>, <1000000>;
25 snps,reset-active-low;
/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi133 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
374 sd_rst: reset {
375 compatible = "socionext,uniphier-pxs3-sd-reset";
376 #reset-cells = <1>;
390 peri_rst: reset {
391 compatible = "socionext,uniphier-pxs3-peri-reset";
392 #reset-cells = <1>;
424 reset-names = "host";
539 sys_rst: reset {
540 compatible = "socionext,uniphier-pxs3-reset";
[all …]
Duniphier-ld20.dtsi174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
357 reset-names = "aio";
417 reset-names = "evea", "exiv", "adamv";
439 adamv_rst: reset {
440 compatible = "socionext,uniphier-ld20-adamv-reset";
441 #reset-cells = <1>;
548 sd_rst: reset {
549 compatible = "socionext,uniphier-ld20-sd-reset";
550 #reset-cells = <1>;
564 peri_rst: reset {
[all …]
Duniphier-ld11.dtsi100 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
232 reset-names = "aio";
292 reset-names = "evea", "exiv", "adamv";
314 adamv_rst: reset {
315 compatible = "socionext,uniphier-ld11-adamv-reset";
316 #reset-cells = <1>;
418 sd_rst: reset {
419 compatible = "socionext,uniphier-ld11-sd-reset";
420 #reset-cells = <1>;
434 peri_rst: reset {
[all …]
/arch/mips/boot/dts/ralink/
Dmt7628a.dtsi19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
142 reset-names = "wdt";
158 reset-names = "intc";
194 reset-names = "spi";
210 reset-names = "i2c";
226 reset-names = "uart0";
242 reset-names = "uart1";
258 reset-names = "uart2";
[all …]
/arch/arm64/boot/dts/nvidia/
Dtegra132.dtsi50 reset-names = "pex", "afi", "pcie_x";
92 reset-names = "host1x";
106 reset-names = "dc";
120 reset-names = "dc";
135 reset-names = "hdmi";
150 reset-names = "sor";
162 reset-names = "dpaux";
196 reset-names = "gpu";
229 #reset-cells = <1>;
246 reset-names = "actmon";
[all …]
/arch/powerpc/platforms/52xx/
Dmpc52xx_common.c284 int reset; in mpc5200_psc_ac97_gpio_reset() local
292 reset = PSC1_RESET; /* AC97_1_RES */ in mpc5200_psc_ac97_gpio_reset()
298 reset = PSC2_RESET; /* AC97_2_RES */ in mpc5200_psc_ac97_gpio_reset()
316 setbits8(&wkup_gpio->wkup_gpioe, reset); in mpc5200_psc_ac97_gpio_reset()
319 setbits8(&wkup_gpio->wkup_ddr, reset); in mpc5200_psc_ac97_gpio_reset()
324 clrbits8(&wkup_gpio->wkup_dvo, reset); in mpc5200_psc_ac97_gpio_reset()
330 setbits8(&wkup_gpio->wkup_dvo, reset); in mpc5200_psc_ac97_gpio_reset()

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