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/arch/mips/alchemy/devboards/
Dplatform.c81 struct resource *sr; in db1x_register_pcmcia_socket() local
90 sr = kcalloc(cnt, sizeof(struct resource), GFP_KERNEL); in db1x_register_pcmcia_socket()
91 if (!sr) in db1x_register_pcmcia_socket()
100 sr[0].name = "pcmcia-attr"; in db1x_register_pcmcia_socket()
101 sr[0].flags = IORESOURCE_MEM; in db1x_register_pcmcia_socket()
102 sr[0].start = pcmcia_attr_start; in db1x_register_pcmcia_socket()
103 sr[0].end = pcmcia_attr_end; in db1x_register_pcmcia_socket()
105 sr[1].name = "pcmcia-mem"; in db1x_register_pcmcia_socket()
106 sr[1].flags = IORESOURCE_MEM; in db1x_register_pcmcia_socket()
107 sr[1].start = pcmcia_mem_start; in db1x_register_pcmcia_socket()
[all …]
/arch/parisc/include/asm/
Duaccess.h28 #define LDD_USER(sr, val, ptr) __get_user_asm64(sr, val, ptr) argument
29 #define STD_USER(sr, x, ptr) __put_user_asm64(sr, x, ptr) argument
31 #define LDD_USER(sr, val, ptr) __get_user_asm(sr, val, "ldd", ptr) argument
32 #define STD_USER(sr, x, ptr) __put_user_asm(sr, "std", x, ptr) argument
62 #define __get_user_internal(sr, val, ptr) \ argument
67 case 1: __get_user_asm(sr, val, "ldb", ptr); break; \
68 case 2: __get_user_asm(sr, val, "ldh", ptr); break; \
69 case 4: __get_user_asm(sr, val, "ldw", ptr); break; \
70 case 8: LDD_USER(sr, val, ptr); break; \
82 #define __get_user_asm(sr, val, ldx, ptr) \ argument
[all …]
Dprocessor.h140 .sr = { 0, }, \
252 regs->sr[2] = LINUX_GATEWAY_SPACE; \
253 regs->sr[3] = 0xffff; \
254 regs->sr[4] = spaceid; \
255 regs->sr[5] = spaceid; \
256 regs->sr[6] = spaceid; \
257 regs->sr[7] = spaceid; \
/arch/arm/mach-omap2/
Dsmartreflex-class3.c15 static int sr_class3_enable(struct omap_sr *sr) in sr_class3_enable() argument
17 unsigned long volt = voltdm_get_voltage(sr->voltdm); in sr_class3_enable()
21 __func__, sr->name); in sr_class3_enable()
25 omap_vp_enable(sr->voltdm); in sr_class3_enable()
26 return sr_enable(sr, volt); in sr_class3_enable()
29 static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset) in sr_class3_disable() argument
31 sr_disable_errgen(sr); in sr_class3_disable()
32 omap_vp_disable(sr->voltdm); in sr_class3_disable()
33 sr_disable(sr); in sr_class3_disable()
35 voltdm_reset(sr->voltdm); in sr_class3_disable()
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/arch/ia64/kernel/
Dunwind.c616 push (struct unw_state_record *sr) in push() argument
625 memcpy(rs, &sr->curr, sizeof(*rs)); in push()
626 sr->curr.next = rs; in push()
630 pop (struct unw_state_record *sr) in pop() argument
632 struct unw_reg_state *rs = sr->curr.next; in pop()
638 memcpy(&sr->curr, rs, sizeof(*rs)); in pop()
746 finish_prologue (struct unw_state_record *sr) in finish_prologue() argument
757 reg = sr->curr.reg + unw.save_order[i]; in finish_prologue()
760 reg->val = sr->gr_save_loc++; in finish_prologue()
770 if (sr->imask) { in finish_prologue()
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/arch/xtensa/variants/csp/include/variant/
Dtie.h114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/arch/xtensa/variants/de212/include/variant/
Dtie.h90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
93 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/arch/parisc/kernel/
Dkgdb.c71 gr->sr0 = regs->sr[0]; in pt_regs_to_gdb_regs()
72 gr->sr1 = regs->sr[1]; in pt_regs_to_gdb_regs()
73 gr->sr2 = regs->sr[2]; in pt_regs_to_gdb_regs()
74 gr->sr3 = regs->sr[3]; in pt_regs_to_gdb_regs()
75 gr->sr4 = regs->sr[4]; in pt_regs_to_gdb_regs()
76 gr->sr5 = regs->sr[5]; in pt_regs_to_gdb_regs()
77 gr->sr6 = regs->sr[6]; in pt_regs_to_gdb_regs()
78 gr->sr7 = regs->sr[7]; in pt_regs_to_gdb_regs()
102 regs->sr[0] = gr->sr0; in gdb_regs_to_pt_regs()
103 regs->sr[1] = gr->sr1; in gdb_regs_to_pt_regs()
[all …]
Dptrace.c449 case RI(sr[0]) ... RI(sr[7]): return regs->sr[num - RI(sr[0])]; in get_reg()
505 case RI(sr[0]) ... RI(sr[7]): return regs->sr[num - RI(sr[0])]; in set_reg()
703 REG_OFFSET_INDEX(sr,0),
704 REG_OFFSET_INDEX(sr,1),
705 REG_OFFSET_INDEX(sr,2),
706 REG_OFFSET_INDEX(sr,3),
707 REG_OFFSET_INDEX(sr,4),
708 REG_OFFSET_INDEX(sr,5),
709 REG_OFFSET_INDEX(sr,6),
710 REG_OFFSET_INDEX(sr,7),
/arch/xtensa/variants/dc232b/include/variant/
Dtie.h94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
/arch/xtensa/variants/dc233c/include/variant/
Dtie.h114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
124 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
124 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
/arch/arm64/kvm/hyp/vhe/
DMakefile9 obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o
10 obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
/arch/mips/sgi-ip27/
Dip27-nmi.c91 pr_emerg("Status: %08lx ", nr->sr); in nmi_cpu_eframe_save()
93 if (nr->sr & ST0_KX) in nmi_cpu_eframe_save()
95 if (nr->sr & ST0_SX) in nmi_cpu_eframe_save()
97 if (nr->sr & ST0_UX) in nmi_cpu_eframe_save()
100 switch (nr->sr & ST0_KSU) { in nmi_cpu_eframe_save()
115 if (nr->sr & ST0_ERL) in nmi_cpu_eframe_save()
117 if (nr->sr & ST0_EXL) in nmi_cpu_eframe_save()
119 if (nr->sr & ST0_IE) in nmi_cpu_eframe_save()
/arch/sh/kernel/
Drelocate_kernel.S39 stc.l sr, @-r15
45 stc sr, r8
47 ldc r8, sr
60 stc sr, r8
62 ldc r8, sr
92 stc sr, r8
94 ldc r8, sr
106 stc sr, r8
108 ldc r8, sr
121 stc sr, r8
[all …]
/arch/csky/include/asm/
Dptrace.h23 #define user_mode(regs) (!((regs)->sr & PS_S))
26 #define trap_no(regs) ((regs->sr >> 16) & 0xff)
42 return ((regs->sr >> 16) & 0xff) == VEC_TRAP0; in in_syscall()
47 regs->sr &= ~(0xff << 16); in forget_syscall()
/arch/powerpc/kernel/
Dsignal_32.c113 __unsafe_restore_general_regs(struct pt_regs *regs, struct mcontext __user *sr) in __unsafe_restore_general_regs() argument
121 unsafe_get_user(gregs[i], &sr->mc_gregs[i], failed); in __unsafe_restore_general_regs()
156 int __unsafe_restore_general_regs(struct pt_regs *regs, struct mcontext __user *sr) in __unsafe_restore_general_regs() argument
159 unsafe_copy_from_user(regs, &sr->mc_gregs, PT_MSR * sizeof(elf_greg_t), failed); in __unsafe_restore_general_regs()
162 unsafe_copy_from_user(&regs->orig_gpr3, &sr->mc_gregs[PT_ORIG_R3], in __unsafe_restore_general_regs()
461 struct mcontext __user *sr, int sig) in restore_user_regs() argument
469 if (!user_read_access_begin(sr, sizeof(*sr))) in restore_user_regs()
477 unsafe_restore_general_regs(regs, sr, failed); in restore_user_regs()
479 unsafe_get_user(msr, &sr->mc_gregs[PT_MSR], failed); in restore_user_regs()
495 unsafe_copy_from_user(&current->thread.vr_state, &sr->mc_vregs, in restore_user_regs()
[all …]
/arch/powerpc/platforms/4xx/
Duic.c55 u32 er, sr; in uic_unmask_irq() local
57 sr = 1 << (31-src); in uic_unmask_irq()
61 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
63 er |= sr; in uic_unmask_irq()
98 u32 er, sr; in uic_mask_ack_irq() local
100 sr = 1 << (31-src); in uic_mask_ack_irq()
103 er &= ~sr; in uic_mask_ack_irq()
114 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
/arch/csky/kernel/
Dptrace.c43 regs->sr = (regs->sr & TRACE_MODE_MASK) | TRACE_MODE_RUN; in singlestep_disable()
46 regs->sr |= BIT(6); in singlestep_disable()
54 regs->sr = (regs->sr & TRACE_MODE_MASK) | TRACE_MODE_SI; in singlestep_enable()
57 regs->sr &= ~BIT(6); in singlestep_enable()
103 regs.sr = (regs.sr & BIT(0)) | (task_pt_regs(target)->sr & ~BIT(0)); in gpr_set()
211 REG_OFFSET_NAME(sr),
487 pr_info("PSR: 0x%08lx\n", (long)fp->sr); in show_regs()
/arch/powerpc/include/asm/book3s/32/
Dmmu-hash.h71 .macro uus_addi sr reg1 reg2 imm
72 .if NUM_USER_SEGMENTS > \sr
77 .macro uus_mtsr sr reg1
78 .if NUM_USER_SEGMENTS > \sr
79 mtsr \sr, \reg1
/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-clock.dtsi33 #include <dt-bindings/clock/bcm-sr.h>
51 compatible = "brcm,sr-genpll0";
63 compatible = "brcm,sr-genpll2";
75 compatible = "brcm,sr-genpll3";
85 compatible = "brcm,sr-genpll4";
97 compatible = "brcm,sr-genpll5";
107 compatible = "brcm,sr-lcpll0";
118 compatible = "brcm,sr-lcpll1";
/arch/powerpc/kvm/
Dbook3s_32_mmu_host.c306 u32 sr; in kvmppc_mmu_map_segment() local
313 svcpu->sr[esid] = SR_INVALID; in kvmppc_mmu_map_segment()
323 sr = map->host_vsid | SR_KP; in kvmppc_mmu_map_segment()
324 svcpu->sr[esid] = sr; in kvmppc_mmu_map_segment()
326 dprintk_sr("MMU: mtsr %d, 0x%x\n", esid, sr); in kvmppc_mmu_map_segment()
338 dprintk_sr("MMU: flushing all segments (%d)\n", ARRAY_SIZE(svcpu->sr)); in kvmppc_mmu_flush_segments()
339 for (i = 0; i < ARRAY_SIZE(svcpu->sr); i++) in kvmppc_mmu_flush_segments()
340 svcpu->sr[i] = SR_INVALID; in kvmppc_mmu_flush_segments()
/arch/sh/kernel/cpu/
Dinit.c232 unsigned long sr; in release_dsp() local
239 : "=&r" (sr) in release_dsp()
246 unsigned long sr; in dsp_init() local
258 : "=&r" (sr) in dsp_init()
263 if (sr & SR_DSP) in dsp_init()
/arch/m68k/coldfire/
Dentry.S62 move #0x2000,%sr /* enable intrs again */
105 move #0x2700,%sr /* disable intrs */
145 move #0x2000,%sr /* enable intrs again */
184 movew %sr,%d1 /* save current status */
198 movew %d7,%sr

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