| /arch/arm64/include/asm/ |
| D | sysreg.h | 37 #define sys_reg(op0, op1, crn, crm, op2) \ macro
42 #define sys_insn sys_reg
125 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
126 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
127 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
128 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
129 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
130 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
131 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
132 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
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| D | arm_dsu_pmu.h | 18 #define CLUSTERPMCR_EL1 sys_reg(3, 0, 15, 5, 0)
19 #define CLUSTERPMCNTENSET_EL1 sys_reg(3, 0, 15, 5, 1)
20 #define CLUSTERPMCNTENCLR_EL1 sys_reg(3, 0, 15, 5, 2)
21 #define CLUSTERPMOVSSET_EL1 sys_reg(3, 0, 15, 5, 3)
22 #define CLUSTERPMOVSCLR_EL1 sys_reg(3, 0, 15, 5, 4)
23 #define CLUSTERPMSELR_EL1 sys_reg(3, 0, 15, 5, 5)
24 #define CLUSTERPMINTENSET_EL1 sys_reg(3, 0, 15, 5, 6)
25 #define CLUSTERPMINTENCLR_EL1 sys_reg(3, 0, 15, 5, 7)
26 #define CLUSTERPMCCNTR_EL1 sys_reg(3, 0, 15, 6, 0)
27 #define CLUSTERPMXEVTYPER_EL1 sys_reg(3, 0, 15, 6, 1)
[all …]
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| D | esr.h | 236 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
248 sys_reg(3, \
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| D | cpufeature.h | 357 u32 sys_reg; member
811 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
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| /arch/arm64/kernel/ |
| D | cpufeature.c | 816 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) in init_cpu_ftr_reg() argument
824 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); in init_cpu_ftr_reg()
1328 val = read_sanitised_ftr_reg(entry->sys_reg); in has_cpuid_feature()
1330 val = __read_sysreg_by_encoding(entry->sys_reg); in has_cpuid_feature()
1802 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), in has_address_auth_cpucap()
1807 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), in has_address_auth_cpucap()
1916 .sys_reg = SYS_ID_AA64PFR0_EL1,
1927 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1940 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1952 .sys_reg = SYS_ID_AA64ISAR0_EL1,
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| /arch/arm/boot/dts/ |
| D | tegra20-tamonten.dtsi | 345 vin-sm0-supply = <&sys_reg>;
346 vin-sm1-supply = <&sys_reg>;
347 vin-sm2-supply = <&sys_reg>;
355 sys_reg: sys { label
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| D | tegra20-paz00.dts | 376 vin-sm0-supply = <&sys_reg>;
377 vin-sm1-supply = <&sys_reg>;
378 vin-sm2-supply = <&sys_reg>;
386 sys_reg: sys { label
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| D | exynos4.dtsi | 178 sys_reg: syscon@10010000 { label
222 samsung,sysreg = <&sys_reg>;
235 samsung,sysreg = <&sys_reg>;
248 samsung,sysreg = <&sys_reg>;
261 samsung,sysreg = <&sys_reg>;
715 samsung,sysreg = <&sys_reg>;
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| D | tegra20-ventana.dts | 410 vin-sm0-supply = <&sys_reg>;
411 vin-sm1-supply = <&sys_reg>;
412 vin-sm2-supply = <&sys_reg>;
420 sys_reg: sys { label
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| D | tegra20-harmony.dts | 327 vin-sm0-supply = <&sys_reg>;
328 vin-sm1-supply = <&sys_reg>;
329 vin-sm2-supply = <&sys_reg>;
337 sys_reg: sys { label
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| D | tegra20-seaboard.dts | 432 vin-sm0-supply = <&sys_reg>;
433 vin-sm1-supply = <&sys_reg>;
434 vin-sm2-supply = <&sys_reg>;
442 sys_reg: sys { label
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| D | tegra20-acer-a500-picasso.dts | 570 vin-sm0-supply = <&sys_reg>;
571 vin-sm1-supply = <&sys_reg>;
572 vin-sm2-supply = <&sys_reg>;
580 sys_reg: sys { label
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| D | exynos3250.dtsi | 167 sys_reg: syscon@10010000 { label
338 samsung,sysreg = <&sys_reg>;
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| D | exynos4412.dtsi | 687 samsung,sysreg-phandle = <&sys_reg>;
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| /arch/arm64/kvm/ |
| D | sys_regs.h | 17 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
|