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Searched refs:tmp1 (Results 1 – 25 of 59) sorted by relevance

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/arch/arm/mach-at91/
Dpm_suspend.S19 tmp1 .req r4 label
81 mcr p15, 0, tmp1, c7, c0, 4
133 ldr tmp1, [r2, #UDDRC_PCTRL_0]
134 bic tmp1, tmp1, #0x1
135 str tmp1, [r2, #UDDRC_PCTRL_0]
137 ldr tmp1, [r2, #UDDRC_PCTRL_1]
138 bic tmp1, tmp1, #0x1
139 str tmp1, [r2, #UDDRC_PCTRL_1]
141 ldr tmp1, [r2, #UDDRC_PCTRL_2]
142 bic tmp1, tmp1, #0x1
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/arch/arm64/include/asm/
Dasm_pointer_auth.h12 .macro __ptrauth_keys_install_kernel_nosync tsk, tmp1, tmp2, tmp3
13 mov \tmp1, #THREAD_KEYS_KERNEL
14 add \tmp1, \tsk, \tmp1
15 ldp \tmp2, \tmp3, [\tmp1, #PTRAUTH_KERNEL_KEY_APIA]
20 .macro ptrauth_keys_install_kernel_nosync tsk, tmp1, tmp2, tmp3
22 __ptrauth_keys_install_kernel_nosync \tsk, \tmp1, \tmp2, \tmp3
26 .macro ptrauth_keys_install_kernel tsk, tmp1, tmp2, tmp3
28 __ptrauth_keys_install_kernel_nosync \tsk, \tmp1, \tmp2, \tmp3
35 .macro __ptrauth_keys_install_kernel_nosync tsk, tmp1, tmp2, tmp3
38 .macro ptrauth_keys_install_kernel_nosync tsk, tmp1, tmp2, tmp3
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Dasm-uaccess.h15 .macro __uaccess_ttbr0_disable, tmp1
16 mrs \tmp1, ttbr1_el1 // swapper_pg_dir
17 bic \tmp1, \tmp1, #TTBR_ASID_MASK
18 sub \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET // reserved_pg_dir
19 msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
21 add \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET
22 msr ttbr1_el1, \tmp1 // set reserved ASID
26 .macro __uaccess_ttbr0_enable, tmp1, tmp2
27 get_current_task \tmp1
28 ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1
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/arch/sparc/include/asm/
Dhead_64.h35 #define BRANCH_IF_SUN4V(tmp1,label) \ argument
36 sethi %hi(is_sun4v), %tmp1; \
37 lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
38 brnz,pn %tmp1, label; \
41 #define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \ argument
42 rdpr %ver, %tmp1; \
44 srlx %tmp1, 32, %tmp1; \
46 cmp %tmp1, %tmp2; \
50 #define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \ argument
51 rdpr %ver, %tmp1; \
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Dpgtsrmmu.h97 #define WINDOW_FLUSH(tmp1, tmp2) \ argument
98 mov 0, tmp1; \
101 add tmp1, 1, tmp1; \
104 99: subcc tmp1, 1, tmp1; \
/arch/arm/mach-tegra/
Dsleep.h81 .macro check_cpu_part_num part_num, tmp1, tmp2
82 mrc p15, 0, \tmp1, c0, c0, 0
83 ubfx \tmp1, \tmp1, #4, #12
85 cmp \tmp1, \tmp2
89 .macro exit_smp, tmp1, tmp2
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
91 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
95 check_cpu_part_num 0xc09, \tmp1, \tmp2
96 mrceq p15, 0, \tmp1, c0, c0, 5
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/arch/arm64/lib/
Dcsum.c63 __uint128_t tmp1, tmp2, tmp3, tmp4; in do_csum() local
65 tmp1 = *(__uint128_t *)ptr; in do_csum()
74 tmp1 += (tmp1 >> 64) | (tmp1 << 64); in do_csum()
78 tmp1 = ((tmp1 >> 64) << 64) | (tmp2 >> 64); in do_csum()
79 tmp1 += (tmp1 >> 64) | (tmp1 << 64); in do_csum()
82 tmp1 = ((tmp1 >> 64) << 64) | (tmp3 >> 64); in do_csum()
83 tmp1 += (tmp1 >> 64) | (tmp1 << 64); in do_csum()
84 tmp1 = ((tmp1 >> 64) << 64) | sum64; in do_csum()
85 tmp1 += (tmp1 >> 64) | (tmp1 << 64); in do_csum()
86 sum64 = tmp1 >> 64; in do_csum()
Dstrlen.S30 #define tmp1 x4 macro
83 and tmp1, srcin, MIN_PAGE_SIZE - 1
85 cmp tmp1, MIN_PAGE_SIZE - 16
96 sub tmp1, data1, zeroones
100 bics has_nul1, tmp1, tmp2
109 clz tmp1, has_nul1
111 add len, len, tmp1, lsr 3
124 sub tmp1, data1, zeroones
126 orr tmp2, tmp1, tmp3
130 sub tmp1, data1, zeroones
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Dstrcmp.S36 #define tmp1 x7 macro
45 eor tmp1, src1, src2
47 tst tmp1, #7
49 ands tmp1, src1, #7
58 sub tmp1, data1, zeroones
61 bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
98 sub tmp1, tmp3, zeroones
100 bic has_nul, tmp1, tmp2
123 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
125 neg tmp1, tmp1 /* Bits to alignment -64. */
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Dstrnlen.S38 tmp1 .req x8 label
54 ands tmp1, srcin, #15
74 sub tmp1, data1, zeroones
78 bic has_nul1, tmp1, tmp2
81 orr tmp1, has_nul1, has_nul2
82 ccmp tmp1, #0, #0, pl /* NZCV = 0000 */
85 cbz tmp1, .Lhit_limit /* No null in final Qword. */
106 CPU_BE( sub tmp1, data2, zeroones )
108 CPU_BE( bic has_nul2, tmp1, tmp2 )
135 add tmp3, tmp3, tmp1
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Dstrncmp.S37 #define tmp1 x8 macro
63 eor tmp1, src1, src2
65 tst tmp1, #7
79 sub tmp1, data1, zeroones
83 bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
111 add tmp1, limit, 8
114 lsl limit, tmp1, #3 /* Bits -> bytes. */
138 sub tmp1, tmp3, zeroones
140 bic has_nul, tmp1, tmp2
238 ldp tmp1, tmp2, [src2], #16
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Dmemcpy.S45 #define tmp1 x14 macro
102 lsr tmp1, count, 1
105 ldrb B_lw, [src, tmp1]
107 strb B_lw, [dstin, tmp1]
151 sub tmp1, dstin, src
152 cbz tmp1, L(copy0)
153 cmp tmp1, count
159 and tmp1, dstin, 15
161 sub src, src, tmp1
162 add count, count, tmp1 /* Count is now 16 too large. */
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/arch/s390/lib/
Duaccess.c64 unsigned long tmp1, tmp2; in copy_from_user_mvcos() local
66 tmp1 = -4096UL; in copy_from_user_mvcos()
86 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcos()
95 unsigned long tmp1, tmp2; in copy_from_user_mvcp() local
97 tmp1 = -256UL; in copy_from_user_mvcp()
121 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcp()
137 unsigned long tmp1, tmp2; in copy_to_user_mvcos() local
139 tmp1 = -4096UL; in copy_to_user_mvcos()
159 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_to_user_mvcos()
168 unsigned long tmp1, tmp2; in copy_to_user_mvcs() local
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/arch/mips/crypto/
Dpoly1305-mips.pl76 my ($in0,$in1,$tmp0,$tmp1,$tmp2,$tmp3,$tmp4) = ($a4,$a5,$a6,$a7,$at,$t0,$t1);
139 subu $tmp1,$zero,$tmp0
142 dsrlv $tmp3,$in1,$tmp1
144 dsrlv $tmp2,$tmp2,$tmp1
147 dsllv $tmp3,$in1,$tmp1
149 dsllv $tmp2,$tmp2,$tmp1
171 and $tmp1,$in0,$tmp0 # byte swap
175 dsll $tmp1,24
180 or $tmp1,$tmp2
190 or $tmp1,$tmp2
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/arch/powerpc/include/asm/book3s/32/
Dmmu-hash.h99 .macro update_user_segments_by_4 tmp1 tmp2 tmp3 tmp4
100 uus_addi 1, \tmp2, \tmp1, 0x111
101 uus_addi 2, \tmp3, \tmp1, 0x222
102 uus_addi 3, \tmp4, \tmp1, 0x333
104 uus_mtsr 0, \tmp1
109 uus_addi 4, \tmp1, \tmp1, 0x444
114 uus_mtsr 4, \tmp1
119 uus_addi 8, \tmp1, \tmp1, 0x444
124 uus_mtsr 8, \tmp1
129 uus_addi 12, \tmp1, \tmp1, 0x444
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/arch/arm/include/asm/
Dtls.h10 .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
13 .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
20 .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
21 ldr \tmp1, =elf_hwcap
22 ldr \tmp1, [\tmp1, #0]
24 tst \tmp1, #HWCAP_TLS @ hardware TLS available?
32 .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
33 mov \tmp1, #0xffff0fff
34 str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
/arch/arc/include/asm/
Duaccess.h172 unsigned long tmp1, tmp2, tmp3, tmp4; in raw_copy_from_user() local
247 "=r"(tmp1), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) in raw_copy_from_user()
271 "=r"(tmp1), "=r"(tmp2) in raw_copy_from_user()
291 : "+r" (res), "+r"(to), "+r"(from), "=r"(tmp1) in raw_copy_from_user()
311 : "+r" (res), "+r"(to), "+r"(from), "=r"(tmp1) in raw_copy_from_user()
329 : "+r" (res), "+r"(to), "+r"(from), "=r"(tmp1) in raw_copy_from_user()
386 "=r"(tmp1), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) in raw_copy_from_user()
399 unsigned long tmp1, tmp2, tmp3, tmp4; in raw_copy_to_user() local
469 "=r"(tmp1), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) in raw_copy_to_user()
493 "=r"(tmp1), "=r"(tmp2) in raw_copy_to_user()
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/arch/m68k/lib/
Dchecksum.c40 unsigned long tmp1, tmp2; in csum_partial() local
118 "=&d" (tmp1), "=&d" (tmp2) in csum_partial()
139 unsigned long tmp1, tmp2; in csum_and_copy_from_user() local
261 "=&d" (tmp1), "=d" (tmp2) in csum_and_copy_from_user()
278 unsigned long tmp1, tmp2; in csum_partial_copy_nocheck() local
366 "=&d" (tmp1), "=&d" (tmp2) in csum_partial_copy_nocheck()
/arch/ia64/lib/
Ddo_csum.S105 #define tmp1 r26 macro
136 add tmp1=buf,len // last byte's address
149 adds tmp2=-1,tmp1 // last-1
150 and lastoff=7,tmp1 // how many bytes off for last element
152 sub tmp1=8,lastoff // complement to lastoff
161 and tmp1=7, tmp1 // make sure that if tmp1==8 -> tmp1=0
165 shl tmp1=tmp1,3 // number of bits
170 shr.u tmask=tmask,tmp1 // build tail mask, mask off ]8,lastoff]
263 zxt4 tmp1=result1[0]
266 add result1[0]=tmp1,tmp2
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/arch/arm/mach-iop32x/include/mach/
Dentry-macro.S26 .macro arch_ret_to_user, tmp1, tmp2
27 mrc p15, 0, \tmp1, c15, c1, 0
28 ands \tmp2, \tmp1, #(1 << 6)
29 bicne \tmp1, \tmp1, #(1 << 6)
30 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/alpha/lib/
Ddivide.S58 #define tmp1 $3 macro
110 stq tmp1,24($30)
142 subq modulus,divisor,tmp1
145 cmovne compare,tmp1,modulus
151 ldq tmp1,24($30)
184 stq tmp1,24($30)
191 subq $31,$27,tmp1
194 cmovlt $28,tmp1,$27
195 ldq tmp1,24($30)
/arch/x86/crypto/
Dcurve25519-x86_64.c768 u64 *tmp1 = p01_tmp1 + (u32)16U; in point_add_and_double() local
773 u64 *a = tmp1; in point_add_and_double()
774 u64 *b = tmp1 + (u32)4U; in point_add_and_double()
775 u64 *ab = tmp1; in point_add_and_double()
776 u64 *dc = tmp1 + (u32)8U; in point_add_and_double()
798 a1 = tmp1; in point_add_and_double()
799 b1 = tmp1 + (u32)4U; in point_add_and_double()
800 d = tmp1 + (u32)8U; in point_add_and_double()
801 c = tmp1 + (u32)12U; in point_add_and_double()
802 ab1 = tmp1; in point_add_and_double()
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/arch/alpha/kernel/
Dtraps.c440 long error, tmp1, tmp2, tmp3, tmp4; in do_entUna() local
463 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) in do_entUna()
467 una_reg(reg) = tmp1|tmp2; in do_entUna()
479 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) in do_entUna()
483 una_reg(reg) = (int)(tmp1|tmp2); in do_entUna()
495 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2) in do_entUna()
499 una_reg(reg) = tmp1|tmp2; in do_entUna()
522 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), in do_entUna()
546 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), in do_entUna()
570 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2), in do_entUna()
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/arch/csky/abiv2/
Dfpu.c152 unsigned long tmp1, tmp2; in save_to_user_fp() local
157 tmp1 = mfcr("cr<1, 2>"); in save_to_user_fp()
160 user_fp->fcr = tmp1; in save_to_user_fp()
202 : "=a"(tmp1), "=a"(tmp2), "=a"(tmp3), in save_to_user_fp()
214 unsigned long tmp1, tmp2; in restore_from_user_fp() local
219 tmp1 = user_fp->fcr; in restore_from_user_fp()
222 mtcr("cr<1, 2>", tmp1); in restore_from_user_fp()
264 : "=a"(tmp1), "=a"(tmp2), "=a"(tmp3), in restore_from_user_fp()
/arch/arm64/kernel/
Dhead.S137 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
138 add \tmp1, \tbl, #PAGE_SIZE
139 phys_to_pte \tmp2, \tmp1
141 lsr \tmp1, \virt, #\shift
143 and \tmp1, \tmp1, \ptrs // table index
144 str \tmp2, [\tbl, \tmp1, lsl #3]
164 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 argument
165 .Lpe\@: phys_to_pte \tmp1, \rtbl
166 orr \tmp1, \tmp1, \flags // tmp1 = table entry
167 str \tmp1, [\tbl, \index, lsl #3]
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