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Searched refs:vcpu_read_sys_reg (Results 1 – 7 of 7) sorted by relevance

/arch/arm64/kvm/
Ddebug.c38 u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1); in save_guest_debug_regs()
53 vcpu_read_sys_reg(vcpu, MDSCR_EL1)); in restore_guest_debug_regs()
190 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); in kvm_arm_setup_debug()
194 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); in kvm_arm_setup_debug()
212 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1); in kvm_arm_setup_debug()
233 if (vcpu_read_sys_reg(vcpu, MDSCR_EL1) & (DBG_MDSCR_KDE | DBG_MDSCR_MDE)) in kvm_arm_setup_debug()
240 trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_read_sys_reg(vcpu, MDSCR_EL1)); in kvm_arm_setup_debug()
Dinject_fault.c90 if (vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE) { in inject_abt32()
97 far = vcpu_read_sys_reg(vcpu, FAR_EL1); in inject_abt32()
Dhypercalls.c40 cycles = systime_snapshot.cycles - vcpu_read_sys_reg(vcpu, CNTVOFF_EL2); in kvm_ptp_get_time()
Dsys_regs.c146 val = vcpu_read_sys_reg(vcpu, r->reg); in access_vm_reg()
169 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; in access_actlr()
329 p->regval = vcpu_read_sys_reg(vcpu, r->reg); in trap_debug_regs()
1298 p->regval = vcpu_read_sys_reg(vcpu, reg); in access_csselr()
1310 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); in access_ccsidr()
/arch/arm64/include/asm/
Dkvm_emulate.h419 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; in kvm_vcpu_get_mpidr_aff()
427 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); in kvm_vcpu_set_be()
439 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); in kvm_vcpu_is_be()
441 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); in kvm_vcpu_is_be()
Dkvm_mmu.h195 return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; in vcpu_has_cache_enabled()
Dkvm_host.h713 #define vcpu_read_sys_reg(vcpu, reg) vcpu_arch_read_sys_reg(&((vcpu)->arch), reg) macro