| /arch/arm64/kvm/hyp/include/hyp/ |
| D | sysreg-sr.h | 86 write_sysreg(ctxt_sys_reg(ctxt, MDSCR_EL1), mdscr_el1); in __sysreg_restore_common_state()
91 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); in __sysreg_restore_user_state()
92 write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); in __sysreg_restore_user_state()
97 write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); in __sysreg_restore_el1_state()
98 write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1); in __sysreg_restore_el1_state()
128 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1); in __sysreg_restore_el1_state()
129 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1); in __sysreg_restore_el1_state()
154 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1); in __sysreg_restore_el1_state()
207 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt); in __sysreg32_restore_state()
208 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und); in __sysreg32_restore_state()
[all …]
|
| D | switch.h | 75 write_sysreg(1 << 30, fpexc32_el2); in __activate_traps_fpsimd32()
83 write_sysreg(1 << 15, hstr_el2); in __activate_traps_common()
92 write_sysreg(0, pmselr_el0); in __activate_traps_common()
93 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); in __activate_traps_common()
97 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); in __activate_traps_common()
102 write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2); in __deactivate_traps_common()
104 write_sysreg(0, hstr_el2); in __deactivate_traps_common()
106 write_sysreg(0, pmuserenr_el0); in __deactivate_traps_common()
113 write_sysreg(hcr, hcr_el2); in ___activate_traps()
196 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2); in kvm_hyp_handle_fpsimd()
[all …]
|
| D | fault.h | 34 write_sysreg(par, par_el1); in __translate_far_to_hpfar()
|
| /arch/arm64/kvm/hyp/nvhe/ |
| D | timer-sr.c | 15 write_sysreg(cntvoff, cntvoff_el2); in __kvm_timer_set_cntvoff()
29 write_sysreg(val, cnthctl_el2); in __timer_disable_traps()
47 write_sysreg(val, cnthctl_el2); in __timer_enable_traps()
|
| D | switch.c | 51 write_sysreg(val, cptr_el2); in __activate_traps()
52 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); in __activate_traps()
95 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); in __deactivate_traps()
101 write_sysreg(cptr, cptr_el2); in __deactivate_traps()
102 write_sysreg(__kvm_hyp_host_vector, vbar_el2); in __deactivate_traps()
135 write_sysreg(pmu->events_host, pmcntenclr_el0); in __pmu_switch_to_guest()
138 write_sysreg(pmu->events_guest, pmcntenset_el0); in __pmu_switch_to_guest()
155 write_sysreg(pmu->events_guest, pmcntenclr_el0); in __pmu_switch_to_host()
158 write_sysreg(pmu->events_host, pmcntenset_el0); in __pmu_switch_to_host()
|
| /arch/arm/include/asm/ |
| D | arch_gicv3.h | 44 write_sysreg(val, a32); \
69 write_sysreg(val, ICC_DIR); in CPUIF_MAP()
84 write_sysreg(val, ICC_CTLR); in gic_write_ctlr()
95 write_sysreg(val, ICC_IGRPEN1); in gic_write_grpen1()
101 write_sysreg(val, ICC_SGI1R); in gic_write_sgi1r()
111 write_sysreg(val, ICC_SRE); in gic_write_sre()
117 write_sysreg(val, ICC_BPR1); in gic_write_bpr1()
127 write_sysreg(val, ICC_PMR); in gic_write_pmr()
|
| /arch/arm64/include/asm/ |
| D | arch_timer.h | 110 write_sysreg(val, cntp_ctl_el0); in arch_timer_reg_write_cp15()
113 write_sysreg(val, cntp_tval_el0); in arch_timer_reg_write_cp15()
119 write_sysreg(val, cntv_ctl_el0); in arch_timer_reg_write_cp15()
122 write_sysreg(val, cntv_tval_el0); in arch_timer_reg_write_cp15()
164 write_sysreg(cntkctl, cntkctl_el1); in arch_timer_set_cntkctl()
|
| D | cpuidle.h | 35 write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
47 write_sysreg(c->daif_bits, daif); \
|
| D | hardirq.h | 44 write_sysreg(___hcr | HCR_TGE, hcr_el2); \
85 write_sysreg(___hcr, hcr_el2); \
|
| D | daifflags.h | 117 write_sysreg(flags, daif); in local_daif_restore()
142 write_sysreg(flags, daif); in local_daif_inherit()
|
| D | mmu_context.h | 34 write_sysreg(task_pid_nr(next), contextidr_el1); in contextidr_thread_switch()
45 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0()
78 write_sysreg(tcr, tcr_el1); in __cpu_set_tcr_t0sz()
|
| D | dcc.h | 37 write_sysreg((unsigned char)c, dbgdtrtx_el0); in __dcc_putchar()
|
| D | uaccess.h | 91 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); in __uaccess_ttbr0_disable()
94 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
115 write_sysreg(ttbr1, ttbr1_el1); in __uaccess_ttbr0_enable()
119 write_sysreg(ttbr0, ttbr0_el1); in __uaccess_ttbr0_enable()
|
| /arch/arm64/kvm/hyp/vhe/ |
| D | switch.c | 65 write_sysreg(val, cpacr_el1); in __activate_traps()
67 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); in __activate_traps()
77 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); in __deactivate_traps()
86 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); in __deactivate_traps()
90 write_sysreg(host_vectors, vbar_el1); in __deactivate_traps()
|
| D | tlb.c | 59 write_sysreg(val, hcr_el2); in __tlb_switch_to_guest()
69 write_sysreg(0, vttbr_el2); in __tlb_switch_to_host()
70 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); in __tlb_switch_to_host()
|
| D | timer-sr.c | 11 write_sysreg(cntvoff, cntvoff_el2); in __kvm_timer_set_cntvoff()
|
| /arch/arm/mm/ |
| D | pmsa-v7.c | 49 write_sysreg(v, RNGNR); in rgnr_write()
57 write_sysreg(v, DRACR); in dracr_write()
63 write_sysreg(v, DRSR); in drsr_write()
69 write_sysreg(v, DRBAR); in drbar_write()
81 write_sysreg(v, IRACR); in iracr_write()
87 write_sysreg(v, IRSR); in irsr_write()
93 write_sysreg(v, IRBAR); in irbar_write()
|
| D | proc-v7-bugs.c | 48 write_sysreg(0, BPIALL); in harden_branch_predictor_bpiall()
53 write_sysreg(0, ICIALLU); in harden_branch_predictor_iciallu()
|
| D | pmsa-v8.c | 37 write_sysreg(v, PRSEL); in prsel_write()
42 write_sysreg(v, PRBAR); in prbar_write()
47 write_sysreg(v, PRLAR); in prlar_write()
|
| /arch/arm64/kernel/ |
| D | process.c | 254 write_sysreg(0, tpidr_el0); in tls_thread_flush()
265 write_sysreg(0, tpidrro_el0); in tls_thread_flush()
399 write_sysreg(next->thread.uw.tp_value, tpidrro_el0); in tls_thread_switch()
401 write_sysreg(0, tpidrro_el0); in tls_thread_switch()
403 write_sysreg(*task_user_tls(next), tpidr_el0); in tls_thread_switch()
|
| D | perf_event.c | 465 write_sysreg(val, pmevcntr##n##_el0)
472 write_sysreg(val, pmevtyper##n##_el0)
487 write_sysreg(val, pmcr_el0); in armv8pmu_pmcr_write()
597 write_sysreg(value, pmccntr_el0); in armv8pmu_write_counter()
628 write_sysreg(hwc->config_base, pmccfiltr_el0); in armv8pmu_write_event_type()
651 write_sysreg(mask, pmcntenset_el0); in armv8pmu_enable_counter()
668 write_sysreg(mask, pmcntenclr_el0); in armv8pmu_disable_counter()
690 write_sysreg(mask, pmintenset_el1); in armv8pmu_enable_intens()
701 write_sysreg(mask, pmintenclr_el1); in armv8pmu_disable_intens()
704 write_sysreg(mask, pmovsclr_el0); in armv8pmu_disable_intens()
[all …]
|
| D | sys_compat.c | 90 write_sysreg(regs->regs[0], tpidrro_el0); in compat_arm_syscall()
|
| D | debug-monitors.c | 41 write_sysreg(mdscr, mdscr_el1); in mdscr_write()
127 write_sysreg(0, osdlr_el1); in clear_os_lock()
128 write_sysreg(0, oslar_el1); in clear_os_lock()
|
| /arch/arm/include/asm/vdso/ |
| D | cp15.h | 27 #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) macro
|
| /arch/arm64/kvm/ |
| D | pmu.c | 73 write_sysreg(val, pmevtyper##idx##_el0); \
135 write_sysreg(val, pmccfiltr_el0); in kvm_vcpu_pmu_write_evtype_direct()
|