Home
last modified time | relevance | path

Searched refs:AFMT_AUDIO_SRC_CONTROL (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_afmt.h38 SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
49 uint32_t AFMT_AUDIO_SRC_CONTROL; member
Ddcn30_afmt.c135 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in afmt3_se_audio_setup()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h63 SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
171 SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
653 uint32_t AFMT_AUDIO_SRC_CONTROL; member
Ddce_stream_encoder.c1267 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in dce110_se_audio_setup()
/drivers/gpu/drm/radeon/
Ddce6_afmt.c120 WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, in dce6_afmt_select_pin()
Dsid.h923 #define AFMT_AUDIO_SRC_CONTROL 0x713c macro
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.h50 SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
122 uint32_t AFMT_AUDIO_SRC_CONTROL; member
Ddcn10_stream_encoder.c1215 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in enc1_se_audio_setup()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h921 #define AFMT_AUDIO_SRC_CONTROL 0x1c4f macro
Ddce_v6_0.c1125 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, in dce_v6_0_audio_select_pin()
Ddce_v10_0.c1222 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
Ddce_v11_0.c1248 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()