/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v8_0.c | 2154 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2164 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2176 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2224 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2326 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2340 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2356 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2412 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2515 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() 2529 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init() [all …]
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D | gfx_v6_0.c | 452 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 480 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 507 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 676 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 716 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 748 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 882 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 910 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 937 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() 1106 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init() [all …]
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D | gfx_v7_0.c | 1075 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1085 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1097 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1145 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1242 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1256 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1271 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1325 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1428 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() 1438 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init() [all …]
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D | sid.h | 1180 # define ARRAY_1D_TILED_THIN1 2 macro
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/drivers/gpu/drm/radeon/ |
D | cik.c | 2377 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2390 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2405 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2420 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2520 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2533 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2548 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2563 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2664 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() 2677 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init() [all …]
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D | evergreen_cs.c | 97 return ARRAY_1D_TILED_THIN1; in evergreen_cs_get_aray_mode() 308 case ARRAY_1D_TILED_THIN1: in evergreen_surface_check() 329 case ARRAY_1D_TILED_THIN1: in evergreen_surface_value_conv_check() 884 surf.mode = ARRAY_1D_TILED_THIN1; in evergreen_cs_track_validate_texture() 891 case ARRAY_1D_TILED_THIN1: in evergreen_cs_track_validate_texture()
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D | si.c | 2551 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init() 2596 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init() 2632 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init() 2766 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init() 2811 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init() 2847 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
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D | sid.h | 1183 # define ARRAY_1D_TILED_THIN1 2 macro
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D | cikd.h | 1221 # define ARRAY_1D_TILED_THIN1 2 macro
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/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_5_1_enum.h | 526 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | bif_5_0_enum.h | 36 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
D | gmc_8_2_enum.h | 526 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | gmc_8_1_enum.h | 36 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/smu/ |
D | smu_8_0_enum.h | 526 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | smu_7_1_0_enum.h | 79 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | smu_7_1_2_enum.h | 86 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | smu_7_1_3_enum.h | 83 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | smu_7_1_1_enum.h | 86 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_6_0_enum.h | 539 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | uvd_5_0_enum.h | 49 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_8_0_enum.h | 36 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | dce_10_0_enum.h | 611 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/oss/ |
D | oss_2_4_enum.h | 221 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | oss_3_0_1_enum.h | 922 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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D | oss_3_0_enum.h | 335 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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