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Searched refs:BIT11 (Results 1 – 18 of 18) sorted by relevance

/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h619 #define RRSR_54M BIT11
765 #define IMR_RDU BIT11 /* Receive Descriptor Unavailable */
781 #define IMR_TXERR BIT11
813 #define PHIMR_HISRE_IND BIT11 /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to …
836 #define PHIMR_TXERR BIT11
889 #define UHIMR_TXERR BIT11
918 #define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set t…
947 #define IMR_TXERR_88E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
1012 #define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll …
Drtl8723b_spec.h232 #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
Dosdep_service.h28 #define BIT11 0x00000800 macro
Drtw_mlme_ext.h55 #define DYNAMIC_BB_PSD BIT11/* ODM_BB_PSD */
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h217 #define IMR_RDU BIT11
242 #define TPPoll_StopVI BIT11
372 #define RRSR_54M BIT11
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h42 #define BIT11 0x00000800 macro
/drivers/staging/rtl8723bs/core/
Drtw_efuse.c258 rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) & (~BIT11)); in efuse_OneByteRead()
312 rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) | (BIT11)); in efuse_OneByteWrite()
/drivers/staging/rtl8723bs/hal/
Dodm_RegDefine11N.h160 #define ODM_BIT_BB_ATC_11N BIT11
Drtl8723b_rf6052.c65 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); in PHY_RF6052SetBandwidth8723B()
DHal8723BReg.h421 #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
Dodm.h377 ODM_BB_PSD = BIT11,
Dodm_DIG.c212 PHY_SetBBReg(pDM_Odm->Adapter, REG_RD_CTRL, BIT11, 1); /* stop counting if EDCCA is asserted */ in odm_AdaptivityInit()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h21 #define BIT11 0x00000800 macro
/drivers/scsi/
Ddc395x.h65 #define BIT11 0x00000800 macro
/drivers/tty/
Dsynclink_gt.c388 #define IRQ_TXUNDER BIT11 /* HDLC */
4209 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()
4210 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4213 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4214 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4282 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()
4283 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()
4286 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4287 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h369 #define RRSR_54M BIT11
/drivers/scsi/lpfc/
Dlpfc_hw4.h739 #define LPFC_SLI4_INTR11 BIT11
/drivers/char/pcmcia/
Dsynclink_cs.c294 #define IRQ_TIMER BIT11 // timer interrupt