Searched refs:C0_G_Y (Results 1 – 4 of 4) sorted by relevance
/drivers/gpu/drm/msm/disp/dpu1/ |
D | dpu_formats.c | 198 C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, 204 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 210 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 216 C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, 222 C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, 228 C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, 234 C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, 240 C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, 246 C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3, 252 C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, [all …]
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D | dpu_hw_mdss.h | 268 C0_G_Y = 0, enumerator
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D | dpu_hw_intf.c | 169 panel_format = (fmt->bits[C0_G_Y] | in dpu_hw_intf_setup_timing_engine()
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D | dpu_hw_sspp.c | 283 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); in dpu_hw_sspp_setup_format()
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