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Searched refs:DATA_SEL (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsoc15d.h188 #define DATA_SEL(x) ((x) << 29) macro
Dvid.h249 #define DATA_SEL(x) ((x) << 29) macro
Dcikd.h367 #define DATA_SEL(x) ((x) << 29) macro
Dgfx_v7_0.c2193 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()
2205 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2234 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
Dsid.h1826 #define DATA_SEL(x) ((x) << 29) macro
Dgfx_v8_0.c6205 DATA_SEL(1) | INT_SEL(0)); in gfx_v8_0_ring_emit_fence_gfx()
6219 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6296 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
Dgfx_v9_0.c5450 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
/drivers/gpu/drm/radeon/
Dnid.h1249 #define DATA_SEL(x) ((x) << 29) macro
Dsid.h1763 #define DATA_SEL(x) ((x) << 29) macro
Dcikd.h1835 #define DATA_SEL(x) ((x) << 29) macro
Dni.c1407 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
Dr600d.h1674 #define DATA_SEL(x) ((x) << 29) macro
Dcik.c3556 DATA_SEL(1) | INT_SEL(0)); in cik_fence_gfx_ring_emit()
3567 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3593 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
Dr600.c2889 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
Dsi.c3391 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()