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Searched refs:DC_HPD_CONTROL (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.h45 SRI(DC_HPD_CONTROL, HPD, id)
143 uint32_t DC_HPD_CONTROL; member
Ddce_link_encoder.c1646 uint32_t addr = HPD_REG(DC_HPD_CONTROL); in dce110_link_encoder_enable_hpd()
1650 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_enable_hpd()
1653 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_enable_hpd()
1660 uint32_t addr = HPD_REG(DC_HPD_CONTROL); in dce110_link_encoder_disable_hpd()
1663 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_disable_hpd()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.h40 SRI(DC_HPD_CONTROL, HPD, id)
81 uint32_t DC_HPD_CONTROL; member
Ddcn10_link_encoder.c1383 HPD_REG_UPDATE(DC_HPD_CONTROL, in dcn10_link_encoder_enable_hpd()
1391 HPD_REG_UPDATE(DC_HPD_CONTROL, in dcn10_link_encoder_disable_hpd()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c358 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v10_0_hpd_init()
400 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v10_0_hpd_fini()
Ddce_v11_0.c376 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v11_0_hpd_init()
417 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v11_0_hpd_fini()