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Searched refs:DEFINE_QBCM (Results 1 – 8 of 8) sorted by relevance

/drivers/interconnect/qcom/
Dsdx55.c80 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
81 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
82 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
83 DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg);
84 DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
85 DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie);
86 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);
87 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
88 DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);
89 DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);
[all …]
Dsm8350.c168 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
169 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
170 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
171 DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss…
172 DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
173 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
174 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
175 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
176 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
177 DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
[all …]
Dsdm845.c149 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
150 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
151 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
152 DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
153 DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
154 DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_un…
155 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
156 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
157 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
158 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_a…
[all …]
Dsm8150.c159 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
160 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
161 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
162 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
163 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_u…
164 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
165 DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
166 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
167 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
168 DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
[all …]
Dsm8250.c169 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
170 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
171 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
172 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
173 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
174 DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
175 DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
176 DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
177 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
178 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
[all …]
Dsc7180.c156 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
157 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
158 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
159 DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
160 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
161 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_a…
162 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_u…
163 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
164 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
165 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
[all …]
Dsc8180x.c169 DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi);
170 DEFINE_QBCM(bcm_mc0, "MC0", false, &slv_ebi);
171 DEFINE_QBCM(bcm_sh0, "SH0", false, &slv_qns_llcc);
172 DEFINE_QBCM(bcm_mm0, "MM0", false, &slv_qns_mem_noc_hf);
173 DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc);
174 DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto);
175 DEFINE_QBCM(bcm_cn0, "CN0", false, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qh…
176 DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm…
177 DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qhm_qup0, &mas_qhm_qup1, &mas_qhm_qup2);
178 DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc);
[all …]
Dbcm-voter.h15 #define DEFINE_QBCM(_name, _bcmname, _keepalive, ...) \ macro