Home
last modified time | relevance | path

Searched refs:DIG_FE_CNTL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h67 SRI(DIG_FE_CNTL, DIG, id), \
168 SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
169 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
170 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
203 SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
304 SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
305 SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
306 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
307 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
314 SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
[all …]
Ddce_stream_encoder.c536 } else if (enc110->regs->DIG_FE_CNTL) { in dce110_stream_encoder_set_stream_attribute_helper()
539 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); in dce110_stream_encoder_set_stream_attribute_helper()
542 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); in dce110_stream_encoder_set_stream_attribute_helper()
545 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); in dce110_stream_encoder_set_stream_attribute_helper()
580 } else if (enc110->regs->DIG_FE_CNTL) { in dce110_stream_encoder_hdmi_set_stream_attribute()
1009 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); in dce110_stream_encoder_dp_unblank()
1509 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1510 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); in setup_stereo_sync()
1519 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1528 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c480 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); in enc1_stream_encoder_set_stream_attribute_helper()
483 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); in enc1_stream_encoder_set_stream_attribute_helper()
486 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); in enc1_stream_encoder_set_stream_attribute_helper()
983 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); in enc1_stream_encoder_dp_unblank()
1456 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
1457 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); in enc1_setup_stereo_sync()
1466 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg()
1475 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg()
Ddcn10_stream_encoder.h54 SRI(DIG_FE_CNTL, DIG, id), \
126 uint32_t DIG_FE_CNTL; member
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_stream_encoder.c398 REG_UPDATE(DIG_FE_CNTL, in enc2_set_dynamic_metadata()
414 REG_UPDATE(DIG_FE_CNTL, in enc2_set_dynamic_metadata()
496 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); in enc2_stream_encoder_dp_unblank()
501 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); in enc2_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.c518 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); in enc3_stream_encoder_dvi_set_stream_attribute()
522 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); in enc3_stream_encoder_dvi_set_stream_attribute()
564 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); in enc3_stream_encoder_hdmi_set_stream_attribute()
568 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); in enc3_stream_encoder_hdmi_set_stream_attribute()
Ddcn30_dio_stream_encoder.h50 SRI(DIG_FE_CNTL, DIG, id), \
108 SRI(DIG_FE_CNTL, DIG, id), \